Revision 19
DS0110
IGLOO nano Low Power Flash FPGAs
with Flash*Freeze Technology
High-Performance Routing Hierarchy
Features and Benefits
Segmented, Hierarchical Routing and Clock Structure
Low Power Advanced I/Os
nanoPower ConsumptionIndustrys Lowest Power 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
1.2 V to 1.5 V Core Voltage Support for Low Power Bank-Selectable I/O Voltagesup to 4 Banks per Chip
Supports Single-Voltage System Operation Single-Ended I/O Standards: LVTTL, LVCMOS
Low Power Active FPGA Operation 3.3V /2.5V / 1.8V /1.5V/1.2V
Flash*Freeze Technology Enables Ultra-Low Power Wide Range Power Supply Voltage Support per JESD8-B,
Consumption while Maintaining FPGA Content Allowing I/Os to Operate from 2.7 V to 3.6 V
Easy Entry to / Exit from Ultra-Low Power Flash*Freeze Mode Wide Range Power Supply Voltage Support per JESD8-12,
Allowing I/Os to Operate from 1.14 V to 1.575 V
Small Footprint Packages
I/O Registers on Input, Output, and Enable Paths
As Small as 3x3 mm in Size
Selectable Schmitt Trigger Inputs
Wide Range of Features
Hot-Swappable and Cold-Sparing I/Os
Programmable Output Slew Rate and Drive Strength
10,000 to 250,000 System Gates
Weak Pull-Up/-Down
Up to 36 kbits of True Dual-Port SRAM
IEEE 1149.1 (JTAG) Boundary Scan Test
Up to 71 User I/Os
Pin-Compatible Packages across the IGLOO Family
Reprogrammable Flash Technology
Clock Conditioning Circuit (CCC) and PLL
130-nm, 7-Layer Metal, Flash-Based CMOS Process
Up to Six CCC Blocks, One with an Integrated PLL
Instant On Level 0 Support
Configurable Phase Shift, Multiply/Divide, Delay
Single-Chip Solution
Capabilities, and External Feedback
Retains Programmed Design When Powered Off
Wide Input Frequency Range (1.5 MHz up to 250 MHz)
250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System
Performance
Embedded Memory
In-System Programming (ISP) and Security 1 kbit of FlashROM User Nonvolatile Memory
SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
ISP Using On-Chip 128-Bit Advanced Encryption Standard
Blocks (1, 2, 4, 9, and 18 organizations)
(AES) Decryption via JTAG (IEEE 1532compliant)
True Dual-Port SRAM (except 18 organization)
FlashLock Designed to Secure FPGA Contents
1.2 V Programming
Enhanced Commercial Temperature Range
Tj = -20C to +85C
1
IGLOO nano Devices
AGLN010 AGLN015 AGLN020 AGLN060 AGLN125 AGLN250
1 1 1 1 1
IGLOO nano-Z Devices
AGLN030Z AGLN060Z AGLN125Z AGLN250Z
System Gates 10,000 15,000 20,000 30,000 60,000 125,000 250,000
Typical Equivalent Macrocells 86 128 172 256 512 1,024 2,048
VersaTiles (D-flip-flops) 260 384 520 768 1,536 3,072 6,144
Flash*Freeze Mode (typical, W) 2 4 4 5 10 16 24
2
RAM Kbits (1,024 bits) 18 36 36
2
4,608-Bit Blocks 4 8 8
FlashROM Kbits (1,024 bits) 1 1 1 1 1 1 1
2
Secure (AES) ISP Yes Yes Yes
2,3
Integrated PLL in CCCs 1 1 1
VersaNet Globals 4 4 4 6 18 18 18
I/O Banks 2 3 3 2 2 2 4
Maximum User I/Os (packaged device) 34 49 52 77 71 71 68
Maximum User I/Os (Known Good Die) 34 52 83 71 71 68
AGLN030 and smaller devices do not support this feature.
October 2015 I
2015 Microsemi Corporation1
IGLOO nano Devices AGLN010 AGLN015 AGLN020 AGLN060 AGLN125 AGLN250
1
1 1 1 1
IGLOO nano-Z Devices
AGLN030Z AGLN060Z AGLN125Z AGLN250Z
Package Pins
UC/CS UC36 UC81, UC81, CS81 CS81 CS81 CS81
QFN QN48 QN68 CS81 QN48, QN68
VQFP QN68 VQ100 VQ100 VQ100 VQ100
Notes:
1. Not recommended for new designs. Few devices/packages are obsoleted. For more information on obsoleted devices/packages, refer
to the PDN 1503 - IGLOO nano Z and ProASIC3 nano Z Families.
2. AGLN030 and smaller devices do not support this feature.
3. AGLN060, AGLN125, and AGLN250 in the CS81 package do not support PLLs.
4. For higher densities and support of additional features, refer to the DS0095: IGLOO Low Power Flash FPGAs Datasheet and IGLOOe
Low-Power Flash FPGAs Datasheet .
I/Os Per Package
1
IGLOO nano Devices AGLN010 AGLN015 AGLN020 AGLN060 AGLN125 AGLN250
1 1 1 1 1
IGLOO nano-Z Devices AGLN030Z AGLN060Z AGLN125Z AGLN250Z
Known Good Die 34 52 83 71 71 68
UC36 23
QN48 3434
QN68 494949
UC81 5266
CS81 5266606060
VQ100 77717168
Notes:
1. Not recommended for new designs.
2. When considering migrating your design to a lower- or higher-density device, refer to the DS0095: IGLOO Low Power Flash
FPGAs Datasheet and IGLOO FPGA Fabric Users Guide to ensure compliance with design and board migration requirements.
3. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of single-
ended user I/Os available is reduced by one.
4. indicates RoHS-compliant packages. Refer toIGLOO nano Ordering Informatio on page IV for the location of the in
the part number. For nano devices, the VQ100 package is offered in both leaded and RoHS-compliant versions. All other
packages are RoHS-compliant only.
Table 1 IGLOO nano FPGAs Package Sizes Dimensions
Packages UC36 UC81 CS81 QN48 QN68 VQ100
Length Width (mm\mm) 3 x 3 4 x 4 5 x 5 6 x 6 8 x 8 14 x 14
2
Nominal Area (mm ) 9 16 25 36 64 196
Pitch (mm) 0.4 0.4 0.5 0.4 0.4 0.5
Height (mm) 0.80 0.80 0.80 0.90 0.90 1.20
II Revision 19