ATSENSE-101/ATSENSE-201(H)/ ATSENSE-301(H) Multi-Channel Sigma-Delta Analog Front End Description ATSENSE-101/ATSENSE-201(H)/ATSENSE-301(H) are multi-channel analog front end devices which integrate three, four or seven simultaneously sampled Sigma-Delta A/D converters, a high-precision voltage reference with up to 10 ppm/C temperature stability (H-versions), a programmable current signal amplification, a temperature sensor and an SPI interface. When used in data acquisition and energy measurement applications in combination with the Microchip ATSAM4C device family that features a dedicated Cortex -M4 processor and metrology library and a variety of sensors including Shunt, CT and Rogowski coils, the ATSENSE-101/ATSENSE-201(H)/ATSENSE-301(H) exceeds ANSI C12.20-2002 and IEC 62053-22 metering accuracy classes of up to 0.2% over 3000:1 current range. Features Analog Front End - Single-phase (ATSENSE-101), Dual-phase (ATSENSE-201(H)) or Poly-phase (ATSENSE-301(H)) Energy Metering Analog Front End Suitable for Microchip MCUs and Metrology Library - Compliant with Class 0.2 Standards (ANSI C12.20-2002 and IEC 62053-22) - Three, Four or Seven Sigma-Delta ADC Measurement Channels: One, Two or Three Voltages, Two or Four Cur- rents, 102 dB Dynamic Range - Current Channels with Pre-Gain (x1, x2, x4, x8) - Supports Shunt, Current Transformer and Rogowski Coils - Dedicated Current Channel for Anti-tamper Measurement - Integrated SINC Decimation Filters. Output Data Rate: 16 kSps typical - Integrated 2.8V LDO Regulator to Supply Analog Functions - 3.0V to 3.6V Operation, Ultra Low Power: < 2.5 mW typical/Channel 3.3V - Specified over two ambient operating temperature ranges : -40C +85C and -40C +105C Precision Voltage Reference - Standard 1.2V Output Voltage with Possible External Bypass - Temperature Drift: 50 ppm typical (ATSENSE-101/ATSENSE-201/ATSENSE-301) - Temperature Drift: 10 ppm typical (ATSENSE-201H/ATSENSE-301H) - Factory-measured Temperature Drift and Die Temperature Sensor to Perform Software Correction - Digital Interface - 8 MHz Serial Peripheral Interface (SPI) Compatible Mode 1 (8-bit) for ADC Data and AFE Controls - Interrupt Output Line Signaling ADC End-of-Conversion, Underrun and Overrun Package - 32-lead TQFP, 7 x 7 x 1.4 mm - 20-lead SOIC, 12.8 x 7.5 x 2.3 mm 2017 Microchip Technology Inc. DS60001524A-page 1ATSENSE-101/ATSENSE-201(H)/ATSENSE-301(H) 1. Block Diagrams Figure 1-1: ATSENSE-301(H) Functional Block Diagram VDDA VP3 GNDA ADCV3 ADC <23:0> VN Decimator 2.8V VDDIN ADCI3 LDO <23:0> IP3 Decimator ADC PGA IN3 Die VREF Voltage Temperature Reference 500 sensor GNDREF VTEMP VP2 ADCV2 ADC <23:0> VN Decimator SPCK NPCS Serial ADCI2 <23:0> Peripheral MISO IP2 Decimator Interface MOSI PGA ADC IN2 Control Registers Interrupt ITOUT VP1 Controller ADCV1 ADC VN <23:0> ROM Decimator (Calibration Data) ADCI1 <23:0> IP1 Decimator PGA ADC IN1 VDDT VDDIO FS CLK (MCLK/OSR) Clock Power ADC CLK Generator On Reset GNDD (MCLK/2) IP0 MCLK IN0 ADCI0 DIFF <23:0> MUX PGA ADC Decimator 2:1 VTEMP ATSENSE-301(H) DS60001524A-page 2 2017 Microchip Technology Inc. VDDA GNDA VREF VDDA GNDA VREF VDDA GNDA VREF VDDA GNDA VREF VDDA GNDA VREF VDDA GNDA VREF VDDA GNDA VREF