ATWILC1000A-MUT IEEE 802.11 b/g/n Link Controller SoC Datasheet Description ATWILC1000A is a single chip IEEE 802.11 b/g/n Radio/Baseband/MAC link controller optimized for low-power mobile applications. ATWILC1000A supports single stream 1x1 802.11n mode providing up to 72Mbps PHY rate. The ATWILC1000A features fully integrated Power Amplifier, LNA, Switch, and Power Management. Implemented in 65nm CMOS technology, the ATWILC1000A offers very low power consumption while simultaneously providing high performance and minimal bill of materials. The ATWILC1000A supports two and three Bluetooth coexistence protocols. The 2 ATWILC1000A provides multiple peripheral interfaces including UART, SPI, I C, and SDIO. The only external clock source needed for the ATWILC1000A is a high-speed crystal or oscillator with a wide range of reference clock frequencies supported (12-40MHz). The ATWILC1000A is available in both QFN and Wafer Level Chip Scale Package (WLCSP) packaging. Features IEEE 802.1 b/g/n 20MHz (1x1) solution Single spatial stream in 2.4GHz ISM band Integrated PA and T/R Switch Superior Sensitivity and Range via advanced PHY signal processing Advanced Equalization and Channel Estimation Advanced Carrier and Timing Synchronization Wi-Fi Direct and Soft-AP support Supports IEEE 802.11 WEP, WPA, WPA2 Security Supports China WAPI security Superior MAC throughput via hardware accelerated two-level A-MSDU/A- MPDU frame aggregation and block acknowledgement On-chip memory management engine to reduce host load 2 SPI, SDIO, UART, and I C host interfaces 2/3 wire Bluetooth coexistence interface Operating temperature range of -40C to +85C Power save modes: <1A Deep Power Down mode typical 3.3V I/O 280A Doze mode with chip settings preserved (used for beacon monitoring) On-chip low power sleep oscillator Fast host wake-up from Doze mode by a pin or host I/O transaction Atmel-42351C-ATWILC1000A-MUT-SmartConnect-Datasheet 022015 Table of Contents 1 Ordering Information and IC Marking ........................................................................ 4 2 Block Diagram ............................................................................................................. 4 3 Pin-Out and Package Information .............................................................................. 4 3.1 Pin Description ...................................................................................................................................... 4 3.2 Package Description ............................................................................................................................. 6 4 Electrical Specifications ............................................................................................. 8 4.1 Absolute Ratings ................................................................................................................................... 8 4.2 Recommended Operating Conditions ................................................................................................... 8 4.3 DC Electrical Characteristics ................................................................................................................. 9 5 Clocking ..................................................................................................................... 9 5.1 Crystal Oscillator ................................................................................................................................... 9 5.2 Low-Power Oscillator .......................................................................................................................... 10 6 CPU and Memory Subsystems ................................................................................. 10 6.1 Processor ............................................................................................................................................ 10 6.2 Memory Subsystem............................................................................................................................. 11 6.3 Non-Volatile Memory (EFuse) ............................................................................................................. 11 7 WLAN Subsystem ...................................................................................................... 11 7.1 MAC .............................................................................................................................................. 12 7.1.1 Features ................................................................................................................................. 12 7.1.2 Description .............................................................................................................................. 12 7.2 PHY .............................................................................................................................................. 13 7.2.1 Features ................................................................................................................................. 13 7.2.2 Description .............................................................................................................................. 13 7.3 Radio .............................................................................................................................................. 13 7.3.1 Receiver Performance ............................................................................................................ 13 7.3.2 Transmitter Performance ........................................................................................................ 15 8 External Interfaces .................................................................................................... 15 2 8.1 I C Slave Interface .............................................................................................................................. 16 2 8.2 I C Master Interface ............................................................................................................................ 17 8.3 SPI Slave Interface.............................................................................................................................. 18 8.4 SPI Master Interface............................................................................................................................ 20 8.5 SDIO Slave Interface........................................................................................................................... 21 8.6 UART .............................................................................................................................................. 23 8.7 Wi-Fi/Bluetooth Coexistence ............................................................................................................... 23 8.8 GPIOs .............................................................................................................................................. 24 9 Power Management ................................................................................................... 24 9.1 Power Architecture .............................................................................................................................. 24 9.2 Power Consumption ............................................................................................................................ 26 9.2.1 Description of Device States ................................................................................................... 26 9.2.2 Controlling the Device States ................................................................................................. 26 9.2.3 Restrictions for Power States ................................................................................................. 26 9.3 Power-Up/Down Sequence ................................................................................................................. 26 ATWILC1000A-MUT DATASHEET 2 2 Atmel-42351C-ATWILC1000A-MUT-SmartConnect-Datasheet 022015