DSC557-03 Crystal-less Two Output PCIe Gen1/2/3 Clock Generator Features General Description Meets PCIe Gen1, Gen2 & Gen3 specs. The DSC557-03 is a crystal-less, two output PCI express clock generator meeting Gen1, Available Output Formats: Gen2, and Gen3 specifications. The clock o HCSL, LVPECL, or LVDS generator uses proven silicon MEMS o HCSL/LVPECL, HCSL/LVDS, LVPECL/LVDS technology to provide 100MHz* differential output clocks with excellent jitter and Wide Temperature Range stability over a wide range of supply o Ext. Industrial: -40 to 105 C voltages and temperatures. By eliminating the external quartz crystal, the DSSC557-03 o Industrial: -40 to 85 C significantly enhances reliability and o Ext. commercial: -20 to 70 C accelerates product development, while meeting stringent clock performance criteria Supply Range of 2.25 to 3.6 V for a variety of communications, storage, Low Power Consumption and networking applications. o 30% lower than competing devices DSC557-03 has an Output Enable / Disable Excellent Shock & Vibration Immunity feature allowing it to disable the outputs o Qualified to MIL-STD-883 when OE is low. The device is available in two different packages a drop-in Available Footprints: replacement 16 pin TSSOP or a space o 16 TSSOP saving 14 pin QFN (77% less board space). o 14 QFN Additional output formats are also available in any combination of LVPECL, LVDS, and Lead Free & RoHS Compliant HCSL. Short Lead Time: 2 Weeks Block Diagram Applications Control Circuitry Communications/Networking o Ethernet CLK0+ Output o 1G, 10GBASE-T/KR/LR/SR, and FcoE MEMS PLL CLK0- Control o Routers and Switches and Divider CLK1- o Gateways, VoIP, Wireless APs OE CLK1+ o Passive Optical Networks Storage o SAN, NAS, SSD, JBOD Embedded Applications * Clk0+/- and Clk1+/- are 100 MHz as per PCIe o Industrial, Medical, and Avionics standards. For other frequencies, please o Security Systems and Office contact the factory. Automation o Digital Sinage, POS and others Consumer Electronics o Smart TV, Bluray, STB DSC557-03 Page 1 MK-QB-P-D-120917-01-2 Crystal-less Two Output PCIe Gen1/2/3 Clock Generator DSC557-03 Specifications (Unless specified otherwise: T=25 C, VDD =3.3V) Parameter Condition Min. Typ. Max. Unit 1 Supply Voltage V 2.25 3.6 V DD EN pin low outputs are Supply Current I 21 23 mA DD disabled EN pin high outputs are 2 Supply Current I enabled 60 mA DD (Two HCSL Outputs) R =50 , F =F =100 MHz L O1 O2 Includes frequency variations 100 Frequency Stability f due to initial tolerance, temp. ppm 50 and power supply voltage 3 Startup Time t 5 ms SU Input Logic Levels Input logic high V 0.75xV - V IH DD Input logic low V - 0.25xV IL DD 4 Output Disable Time t 5 ns DA Output Enable Time t 20 ns EN 2 Pull-Up Resistor Pull-up on OE pin 40 k 6 HCSL Outputs Parameter Condition Min. Typ. Max. Unit Output Logic Levels Output logic high V R =50 0.725 - V OH L Output logic low V - 0.1 OL Pk to Pk Output Swing Single-Ended 750 mV 4 Output Transition time 20% to 80% Rise Time t 200 400 ps R R =50, C = 2pF L L Fall Time t F 7 Frequency f Single Frequency 2.3 100 460 MHz 0 Output Duty Cycle SYM Differential 48 52 % 5 Period Jitter J F =F =100 MHz 2.5 ps PER O1 O2 RMS PCIe Gen 1.1 R 0.540 Ps J RMS T =D + 14.069 x R (BER 10-12) J J J 8 D PCIe Gen 1.1 0.832 41.9 J ps Jitter, Phase 8 p-p T T =D + 14.069 x R (BER 10-12) 8.536 86.0 J J J J (Common Clock Architecture) PCIe Gen 2.1, 1.5 MHz to 8 J 0.458 3.1 ps RMS-CCHF RMS Nyquist 8 J PCIe Gen 2.1, 10 kHz to 1.5 MHz 0.030 3.0 ps RMS-CCLF RMS 8 J PCIe Gen 3.0 0.165 1.0 ps RMS-CC RMS PCIe Gen 2.1, 1.5 MHz to 8 J 0.561 4.0 ps Integrated Phase Noise RMS-DCHF RMS Nyquist (Data Clock 8 J PCIe Gen 2.1, 10 kHz to 1.5 MHz 1.778 7.5 ps RMS-DCLF RMS Architecture) 8 J PCIe Gen 3.0 0.147 1.0 ps RMS-DC RMS Notes: 1. V should be filtered with 0.01uf capacitor. DD 2. Output is enabled if OE pin is floated or not connected. 3. t is time to 100PPM stable output frequency after V is applied and outputs are enabled. su DD 4. Output Waveform and Connection Diagram define the parameters. 5. Period Jitter includes crosstalk from adjacent output. 6. Contact Sales Discera.com for alternate output options (LVPECL, LVDS, LVCMOS). 7. Contact Sales Discera.com for alternative frequency options 8. Jitter limits established by Gen 1.1, Gen 2.1, and Gen 3.0 PCIe standards. DSC557-03 Page 2 MK-QB-P-D-120917-01-2