LAN9313/LAN9313i Three Port 10/100 Managed Ethernet Switch with MII - Full and half duplex support Highlights - Full duplex flow control High performance and full featured 3 port switch - Backpressure (forced collision) half duplex with VLAN, QoS packet prioritization, Rate Limit- flow control ing, IGMP monitoring and management functions - Automatic flow control based on programma- 2 Serial management via SPI/I C or SMI ble levels Unique Virtual PHY feature simplifies software - Automatic 32-bit CRC generation and check- development by mimicking the multiple switch ing ports as a single port PHY - 2K Jumbo packet support Integrated IEEE 1588 Hardware Time Stamp Unit - Programmable interframe gap, flow control pause value Target Applications - Full transmit/receive statistics Cable, satellite, and IP set-top boxes - Auto-negotiation Digital televisions - Automatic MDI/MDI-X Digital video recorders - Loop-back mode VoIP/Video phone systems Serial Management Home gateways 2 - SPI/I C (slave) access to all internal registers Test/Measurement equipment - MIIM (MDIO) access to PHY related registers Industrial automation systems - SMI (extended MIIM) access to all internal Key Benefits registers IEEE 1588 Hardware Time Stamp Unit Ethernet Switch Fabric - Global 64-bit tunable clock - 32K buffer RAM - Master or slave mode per port - 1K entry forwarding table - Time stamp on TX or RX of Sync and - Port based IEEE 802.1Q VLAN support (16 Delay req packets per port, Timestamp on groups) GPIO - Programmable IEEE 802.1Q tag insertion/removal - 64-bit timer comparator event generation - IEEE 802.1d spanning tree protocol support (GPIO or IRQ) - QoS/CoS Packet prioritization - 4 dynamic QoS queues per port Other Features - Input priority determined by VLAN tag, DA lookup, - General Purpose Timer 2 TOS, DIFFSERV or port default value - Serial EEPROM interface (I C master or - Programmable class of service map based on input Microwire master) for non-managed config- priority uration - Remapping of 802.1Q priority field on per port basis - Programmable GPIOs/LEDs - Programmable rate limiting at the ingress/egress Single 3.3V power supply ports with random early discard, per port / priority Available in Commercial & Industrial Temp. - IGMP v1/v2/v3 monitoring for Multicast Ranges packet filtering - Programmable filter by MAC address Switch Management - Port mirroring/monitoring/sniffing: ingress and/or egress traffic on any ports or port pairs - Fully compliant statistics (MIB) gathering counters - Control registers configurable on-the-fly Ports - 2 internal 10/100 PHYs with HP Auto-MDIX support - 1 MII - PHY mode or MAC mode - Fully compliant with IEEE 802.3 standards - 10BASE-T and 100BASE-TX support 2008-2016 Microchip Technology Inc. DS00002288A-page 1LAN9313/LAN9313i TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: