Data Sheet November 2016 MAX24287 1Gbps Parallel-to-Serial MII Converter General Description Highlighted Features The MAX24287 is a flexible, low-cost Ethernet Bidirectional Wire-Speed Ethernet Interface interface conversion IC. The parallel interface can be Conversion configured for GMII, RGMII, TBI, RTBI, or 10/100 MII, Can Interface Directly to SFP Modules and while the serial interface can be configured for SGMII PHY and Switch ICs 1.25Gbps SGMII or 1000BASE-X operation. In Serial Interface Configurable as 1000BASE-X or SGMII mode, the device interfaces directly to SGMII Revision 1.8 (4-, 6-, or 8-Pin) Ethernet switch ICs, ASIC MACs, and 1000BASE-T electrical SFP modules. In 1000BASE-X mode, the Parallel Interface Configurable as GMII, RGMII, device interfaces directly to 1Gbps 1000BASE-X SFP TBI, RTBI, or 10/100 MII optical modules. The MAX24287 performs automatic Serial Interface Has Clock and Data Recovery translation of link speed and duplex autonegotiation Block (CDR) and Does Not Require a Clock between parallel MII MDIO and the serial interface. Input Translates Link Speed and Duplex Mode This device is ideal for interfacing single-channel Negotiation Between MDIO and SGMII PCS GMII/MII devices such as microprocessors, FPGAs, network processors, Ethernet-over-SONET or -PDH Supports 10/100 MII or RGMII Operation with mappers, and TDM-over-packet circuit emulation SGMII Running at the Same Rate devices. The device also provides a convenient Configurable for 10/100 MII DTE or DCE solution to interface such devices with electrical or Modes (i.e., Connects to PHY or MAC) optical Ethernet SFP modules. Can Also Be Configured as General-Purpose Applications 1:10 SerDes with Optional Comma Alignment Supports Synchronous Ethernet by Providing Any System with a Need to Interface a Component a 25MHz or 125MHz Recovered Clock and with a Parallel MII Interface (GMII, RGMII, TBI RTBI, Accepting a Transmit Clock 10/100 MII) to a Component with an SGMII or Can Provide a 125MHz Clock for the MAC to 1000BASE-X Interface Use as GTXCLK Switches and Routers Accepts 10MHz, 12.8MHz, 25MHz or 125MHz Telecom Equipment Reference Clock Ordering Information Software Control Through MDIO Interface GPIO Pins Can Be Configured as Clocks, PART TEMP RANGE PIN-PACKAGE Status Signals and Interrupt Outputs MAX24287ETK+ -40 C to +85 C 68 TQFN-EP* 1.2V Operation with 3.3V I/O 68 TQFN-EP* MAX24287ETK+T -40 C to +85 C Tape and Reel Small, 8mm x 8mm, 68-Pin TQFN Package +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Block Diagram appears on page 7. Register Map appears on page 42. 1 MAX24287 Table of Contents 1. APPLICATION EXAMPLES .......................................................................................................... 6 2. BLOCK DIAGRAM ........................................................................................................................ 7 3. DETAILED FEATURES ................................................................................................................. 7 4. ACRONYMS, ABBREVIATIONS, AND GLOSSARY .................................................................... 8 5. PIN DESCRIPTIONS ..................................................................................................................... 8 6. FUNCTIONAL DESCRIPTION .................................................................................................... 17 6.1 PIN CONFIGURATION DURING RESET ........................................................................................... 17 6.2 GENERAL-PURPOSE I/O .............................................................................................................. 18 6.2.1 Receive Recovered Clock Squelch Criteria ......................................................................................... 19 6.3 RESET AND PROCESSOR INTERRUPT ........................................................................................... 19 6.3.1 Reset .................................................................................................................................................... 19 6.3.2 Processor Interrupts ............................................................................................................................. 19 6.4 MDIO INTERFACE ....................................................................................................................... 20 6.4.1 MDIO Overview .................................................................................................................................... 20 6.4.2 Examples of MAX24287 and PHY Management Using MDIO ............................................................ 22 6.5 SERIAL INTERFACE 1000BASE-X OR SGMII ............................................................................. 24 6.6 PARALLEL INTERFACE GMII, RGMII, TBI, RTBI, MII .................................................................. 25 6.6.1 GMII Mode ........................................................................................................................................... 25 6.6.2 TBI Mode .............................................................................................................................................. 26 6.6.3 RGMII Mode ......................................................................................................................................... 27 6.6.4 RTBI Mode ........................................................................................................................................... 29 6.6.5 MII Mode .............................................................................................................................................. 30 6.7 AUTO-NEGOTIATION (AN) ........................................................................................................... 31 6.7.1 1000BASE-X Auto-Negotiation ............................................................................................................ 31 6.7.2 SGMII Control Information Transfer ..................................................................................................... 33 6.8 DATA PATHS .............................................................................................................................. 36 6.8.1 GMII, RGMII and MII Serial to Parallel Conversion and Decoding ...................................................... 36 6.8.2 GMII, RGMII and MII Parallel to Serial Conversion and Encoding ...................................................... 36 6.8.3 TBI, RTBI Serial to Parallel Conversion and Decoding ....................................................................... 36 6.8.4 TBI Parallel to Serial Conversion and Encoding .................................................................................. 36 6.8.5 Rate Adaption Buffers, Jumbo Packets and Clock Frequency Differences ......................................... 36 6.9 TIMING PATHS ............................................................................................................................ 37 6.9.1 RX PLL ................................................................................................................................................. 38 6.9.2 TX PLL ................................................................................................................................................. 38 6.9.3 Input Jitter Tolerance ........................................................................................................................... 38 6.9.4 Output Jitter Generation ....................................................................................................................... 38 6.9.5 TX PLL Jitter Transfer .......................................................................................................................... 38 6.9.6 GPIO Pins as Clock Outputs ................................................................................................................ 39 6.10 LOOPBACKS ............................................................................................................................ 39 6.10.1 Diagnostic Loopback ............................................................................................................................ 39 6.10.2 Terminal Loopback ............................................................................................................................... 39 6.10.3 Remote Loopback ................................................................................................................................ 39 6.11 DIAGNOSTIC AND TEST FUNCTIONS .......................................................................................... 40 6.12 DATA PATH LATENCIES ............................................................................................................ 40 6.13 POWER SUPPLY CONSIDERATIONS ........................................................................................... 40 6.14 STARTUP PROCEDURE ............................................................................................................ 41 7. REGISTER DESCRIPTIONS ....................................................................................................... 42 7.1 REGISTER MAP .......................................................................................................................... 42 2