MCP3913 3V Six-Channel Analog Front End Features Description Six Synchronous Sampling 24-Bit Resolution The MCP3913 is a 3V six-channel Analog Front End Delta-Sigma A/D Converters (AFE), containing six synchronous sampling Delta- Sigma, Analog-to-Digital Converters (ADC), six PGAs, 94.5 dB SINAD, -107 dBc Total Harmonic th phase delay compensation block, low-drift internal volt- Distortion (THD) (up to 35 Harmonic), 112 dBFS age reference, Digital Offset and Gain Error Calibration SFDR for Each Channel registers and high-speed 20 MHz SPI-compatible serial Enables 0.1% Typical Active Power Measurement interface. Error Over a 10,000:1 Dynamic Range The MCP3913 ADCs are fully configurable with features Advanced Security Features: such as: 16/24-bit resolution, Oversampling Ratio - 16-Bit Cyclic Redundancy Check (CRC) (OSR) from 32 to 4096, gain from 1x to 32x, indepen- Checksum on All Communications for Secure dent shutdown and Reset, dithering and auto-zeroing. Data Transfers The communication is largely simplified with 8-bit - 16-Bit CRC Checksum and Interrupt Alert for commands, including various continuous Read/Write Register Map Configuration modes and 16/24/32-bit data formats that can be - Register Map Lock with 8-Bit Secure Key accessed by the Direct Memory Access (DMA) of an 8, , DV 2.7V-3.6V AV 16 or 32-bit MCU, and with the separate Data Ready DD DD pin that can directly be connected to an Interrupt Programmable Data Rate Up to 125 ksps: Request (IRQ) input of an MCU. - 4 MHz Maximum Sampling Frequency - 16 MHz Maximum Master Clock The MCP3913 includes advanced security features to secure the communications and the configuration set- Oversampling Ratio Up to 4096 tings, such as a CRC-16 checksum on both serial data Ultra-Low Power Shutdown Mode with <10 A outputs and static register map configuration. It also -122 dB Crosstalk Between Channels includes a register map lock through an 8-bit secure key Low Drift 1.2V Internal Voltage Reference: to stop unwanted WRITE commands from processing. 9 ppm/C The MCP3913 is capable of interfacing with a variety of Differential Voltage Reference Input Pins voltage and current sensors, including shunts, Current High-Gain PGA on Each Channel (up to 32 V/V) Transformers, Rogowski coils and Hall effect sensors. Phase Delay Compensation with 1 s Time Resolution Applications Separate Data Ready Pin for Easy Polyphase Energy Meters Synchronization Energy Metering and Power Measurement Individual 24-Bit Digital Offset and Gain Error Automotive Correction for Each Channel Portable Instrumentation High-Speed 20 MHz SPI Interface with Mode 0,0 and 1,1 Compatibility Medical and Power Monitoring Continuous Read/Write Modes for Minimum Audio/Voice Recognition Communication Time with Dedicated 16/32-Bit Modes Available in a 40-Lead UQFN and 28-Lead SSOP Packages Extended Temperature Range: -40C to +125C 2013-2020 Microchip Technology Inc. DS20005227C-page 1MCP3913 Package Type MCP3913 MCP3913 SSOP 5x5 UQFN* AV DV DD 1 28 40 39 35 33 32 31 DD 38 37 36 34 CH0+ 2 27 RESET CH2+ 1 30 SDI CH0- 26 SDI 3 CH2- 2 29 SDO CH1- 4 SDO 25 CH3- 3 28 SCK CH1+ SCK 5 24 CH3+ 4 27 CS CH2+ 6 23 CS EP NC 5 26 OSC2 41 CH2- 7 22 OSC2 NC 6 25 OSC1/CLKI CH3- 8 21 OSC1/CLKI D CH4+ 7 24 GND D CH3+ 9 20 GND CH4- 8 23 NC CH4+ 10 19 NC CH5- 9 22 DR CH4- DR 11 18 CH5+ D 10 21 GND D CH5- 12 17 GND 11 12 13 14 15 16 17 18 19 20 A CH5+ 13 16 GND REFIN+/OUT 14 15 REFIN- * Includes Exposed Thermal Pad (EP) see Table 3-1. Functional Block Diagram AVDD DVDD REFIN+/OUT Voltage VREFEXT AMCLK Xtal Oscillator Reference OSC1 MCLK Clock + Vref Generation DMCLK/DRCLK OSC2 - REFIN- Vref- Vref+ DMCLK OSR<2:0> OSR/2- OFFCAL CH0 GAINCAL CH0 PRE<1:0> PHASE1 <11:0> <23:0> <23:0> CH0+ + + X MOD<3:0> DATA CH0<23:0> CH0- - 3 PGA Phase SINC + Offset Gain 1 Modulator Shifter SINC Cal. Cal. OFFCAL CH1 GAINCAL CH1 <23:0> <23:0> OSR/2 CH1+ + X + MOD<7:4> DATA CH1<23:0> CH1- - 3 PGA Phase SINC + Offset Gain 1 Modulator Shifter SINC Cal. Cal. OSR/2- OFFCAL CH2 GAINCAL CH2 PHASE1 <23:12> <23:0> <23:0> CH2+ + X + MOD<11:8> DATA CH2<23:0> - CH2- 3 PGA Phase SINC + Offset Gain 1 Modulator Shifter SINC Cal. Cal. Digital SPI OFFCAL CH3 GAINCAL CH3 <23:0> <23:0> Interface OSR/2 CH3+ + DR + X MOD<15:12> SDO DATA CH3<23:0> CH3- - 3 PGA Phase SINC + Offset Gain 1 Modulator Shifter SINC Cal. Cal. RESET OFFCAL CH4 GAINCAL CH4 OSR/2- SDI <23:0> <23:0> PHASE0<11:0> SCK CH4+ + + X CS MOD<19:16> DATA CH4<23:0> CH4- - 3 PGA Phase SINC + Offset Gain 1 Modulator Shifter SINC Cal. Cal. OFFCAL CH5 GAINCAL CH5 <23:0> <23:0> OSR/2 CH5+ + X + MOD<23:20> DATA CH5<23:0> - CH5- 3 PGA Phase SINC + Offset Gain 1 Modulator Shifter SINC Cal. Cal. POR POR AVDD DVDD Monitoring Monitoring ANALOG DIGITAL A GND DGND DS20005227C-page 2 2013-2020 Microchip Technology Inc. NC CH1+ NC CH1- CH0- NC CH0+ NC REFIN+/ A GND OUT AV DD REFIN- NC A GND DV DD AV DD D GND NC RESET DV DD