MCP3919 3V Three-Channel Analog Front End Features: Description: Three Synchronous Sampling 24-Bit Resolution The MCP3919 is a 3V three-channel Analog Front End Delta-Sigma A/D Converters (AFE) containing three synchronous sampling Delta- 93.5 dB SINAD, -107 dBc Total Harmonic Sigma Analog-to-Digital Converters (ADC), three PGAs, th phase delay compensation block, low-drift internal volt- Distortion (THD) (up to 35 Harmonic), 112 dBFS age reference, Digital Offset and Gain Error Calibration SFDR for Each Channel registers, and high-speed 20 MHz SPI-compatible serial Enables 0.1% Typical Active Power Measurement interface. Error Over a 10,000:1 Dynamic Range The MCP3919 ADCs are fully configurable with Advanced Security Features: features, such as: 16/24-bit resolution, Oversampling - 16-Bit Cyclic Redundancy Check (CRC) Ratio (OSR) from 32 to 4096, gain from 1x to 32x, Checksum on All Communications for Secure independent shutdown and Reset, dithering and auto- Data Transfers zeroing. The communication is largely simplified with - 16-Bit CRC Checksum and Interrupt Alert for 8-bit commands, including various continuous Read/ Register Map Configuration Write modes and 16/24/32-bit data formats that can be - Register Map Lock with 8-Bit Secure Key accessed by the Direct Memory Access (DMA) of an 8, , DV 2.7V-3.6V AV DD DD 16 or 32-bit MCU. A separate Data Ready pin is also Programmable Data Rate Up to 125 ksps: included that can directly be connected to an Interrupt Request (IRQ) input of an MCU. - 4 MHz Maximum Sampling Frequency - 16 MHz Maximum Master Clock The MCP3919 includes advanced security features to secure the communications and the configuration Oversampling Ratio Up to 4096 settings, such as a CRC-16 checksum on both serial Ultra Low-Power Shutdown Mode with < 10 A data outputs and static register map configuration. It -122 dB Crosstalk Between Channels also includes a register map lock through an 8-bit Low-Drift 1.2V Internal Voltage Reference: secure key to stop unwanted WRITE commands from 9 ppm/C processing. Differential Voltage Reference Input Pins The MCP3919 is capable of interfacing with a variety of High-Gain PGA on Each Channel (up to 32 V/V) voltage and current sensors, including shunts, Current Phase Delay Compensation with 1 s Time Transformers (CTs), Rogowski coils and Hall effect Resolution sensors. Separate Data Ready Pin for Easy Synchronization Applications: Individual 24-Bit Digital Offset and Gain Error Polyphase Energy Meters Correction for Each Channel Energy Metering and Power Measurement High-Speed 20 MHz SPI Interface with Mode 0,0 Automotive and 1,1 Compatibility Portable Instrumentation Continuous Read/Write Modes for Minimum Communication Time with Dedicated 16/32-Bit Medical and Power Monitoring Modes Audio/Voice Recognition Available in a 28-Lead 5 x 5 mm QFN and 28-Lead SSOP Packages Extended Temperature Range: -40C to +125C 2014-2020 Microchip Technology Inc. DS20005347C-page 1MCP3919 Package Type MCP3919 MCP3919 SSOP 5x5 mm QFN* AV DV DD 1 28 DD CH0+ 2 27 RESET/OSR0 CH0- 26 3 SDI/OSR1 28 27 26 25 24 23 22 CH1- SDO 4 25 CH1+ 5 24 SCK/MCLK CH1- 1 21 SDI/OSR1 CH2+ 6 23 CS/BOOST 20 SDO CH1+ 2 CH2- 7 22 OSC2/MODE CH2+ 3 19 SCK/MCLK EP NC 8 21 OSC1/CLKI/GAIN0 CH2- 4 18 CS/BOOST 29 NC 9 20 D GND NC 17 OSC2/MODE 5 NC 19 NC 10 16 OSC1/CLKI/GAIN0 NC 6 NC 11 18 DR/GAIN1 D 15 NC 7 GND D NC 12 17 GND 89 10 11 12 13 14 A NC 13 16 GND REFIN+/OUT 15 REFIN- 14 *Includes Exposed Thermal Pad (EP) see Table 3-1. Functional Block Diagram AV DV DD DD REFIN+/OUT Voltage AMCLK VREFEXT Xtal Oscillator Reference OSC1/CLK1/GAIN0 MCLK Clock + Vref Generation OSC2/MODE DMCLK/DRCLK - REFIN- Vref- Vref+ DMCLK OSR<2:0> OFFCAL CH0 GAINCAL CH0 OSR/2- PRE<1:0> <23:0> <23:0> PHASE1 <11:0> CH0+ + X + MOD<3:0> - DATA CH0<23:0> CH0- 3 PGA Phase SINC + Offset Gain 1 Modulator Shifter SINC Cal. Cal. OFFCAL CH1 GAINCAL CH1 OSR/2 <23:0> <23:0> CH1+ + + X MOD<7:4> - DATA CH1<23:0> CH1- 3 PGA Phase SINC + Offset Gain 1 Modulator Shifter SINC Cal. Cal. Digital SPI OSR/2- OFFCAL CH2 GAINCAL CH2 Interface DR/GAIN1 PHASE1 <23:12> <23:0> <23:0> SDO CH2+ + X MOD<11:8> - DATA CH2<23:0> CH2- RESET/OSR0 3 PGA Phase SINC + Offset Gain 1 SDI/OSR1 Modulator Shifter SINC Cal. Cal. SCK/MCLR CS/BOOST POR POR AV DV DD DD Monitoring Monitoring ANALOG DIGITAL A GND D GND DS20005347C-page 2 2014-2020 Microchip Technology Inc. REFIN+/ CH0- OUT CH0+ REFIN- A A GND GND AV AV DD DD DV DV DD DD D GND D GND RESET/OSR0 DR/GAIN1