SCH5027E Super I/O with Temperature Sensing, Quiet Auto Fan and Glue Logic with PECI Serial Ports Product Features - Two Full Function Serial Ports General Features - High Speed NS16C550A Compatible UARTs - 3.3 Volt Operation (SIO Block is 5 Volt Toler- with Send/Receive 16-Byte FIFOs ant) - Supports 230k and 460k Baud - LPC Interface - Programmable Baud Rate Generator - Programmable Wake-up Event Interface - Modem Control Circuitry - PC99, PC2001 Compliant - 480 Address and 15 IRQ Options - ACPI 2.0 Compliant Infrared Port - Multiplexed Command, Address and Data - Multiprotocol Infrared Interface Bus - IrDA 1.0 Compliant - Serial IRQ Interface Compatible with Serial- - SHARP ASK IR ized IRQ Support for PCI Systems - 480 Addresses, Up to 15 IRQ - PME Interface Multi-Mode Parallel Port with ChiProtect - ISA Plug-and-Play Compatible Register Set - 25 General Purpose Input/Output Pins - Standard Mode IBM PC/XT, PC/AT, and - System Management Interrupt PS/2 Compatible Bi-directional Parallel o C to - Operating Temperature Range of 0 Port o +70 C - Enhanced Parallel Port (EPP) Compatible - EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant) PECI Interface - IEEE 1284 Compliant Enhanced Capabilities - Supports PECI REQUEST and PECI AVAIL- Port (ECP) ABLE signaling - ChiProtect Circuitry for Protection AC Power Failure Recovery - 960 Address, Up to 15 IRQ and Three DMA Watchdog Timer Options 2.88MB Super I/O Floppy Disk Controller Keyboard Controller - Licensed CMOS 765B Floppy Disk Controller - 8042 Software Compatible - Software and Register Compatible with - 8 Bit Microcomputer Microchip s Proprietary 82077AA Compatible - 2k Bytes of Program ROM Core - 256 Bytes of Data RAM - Supports One Floppy Drive - Four Open Drain Outputs Dedicated for Key- - Configurable Open Drain/Push-Pull Output board/Mouse Interface Drivers - Asynchronous Access to Two Data Registers - Supports Vertical Recording Format and One Status Register - 16-Byte Data FIFO - Supports Interrupt and Polling Access - 100% IBM Compatibility - 8 Bit Counter Timer - Detects All Overrun and Underrun Conditions - Port 92 Support - Sophisticated Power Control Circuitry (PCC) - Fast Gate A20 and KRESET Outputs Including Multiple Powerdown Modes for Motherboard GLUE Logic Reduced Power Consumption - IDE Reset Output - DMA Enable Logic - (4) Buffered PCI Reset Outputs with software - Data Rate and Drive Control Registers controlled reset capability - default transpar- - 480 Address, Up to Eight IRQ and Three ent DMA Options - Front Panel Reset Debouncing and Power - Support 3 Mode FDD Good Signal Generation Enhanced Digital Data Separator - Power Supply Turn On Circuitry with Support - 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 for power button on PS/2 Keyboard Kbps Data Rates - Resume Reset Signal Generation - Programmable Precompensation Modes 2014 Microchip Technology Inc. DS00001784A-page 1SCH5027E - SMBus Isolation Circuitry (2 sets external PECI implementation in the SCH5027E includes sup- and 1 set internal for Hardware Monitoring port for the PECI REQUEST and PECI AVAILABLE Block) signals that are used to wake processors from the C3/ - SMBus 2.0 compliant interface for Hardware C4sleep states. There are three pulse width modulation Monitoring (PWM) outputs with high frequency support that may - LED Control (2) be controlled by the auto fan block, as well as four fan tachometer inputs. There are two additional software Fan Control controlled PWM inputs with associated tachometer - 5 PWM (Pulse width Modulation) Outputs inputs that may be used to monitor fans. The - Low frequency and high frequency PWM nHWM INT pin is implemented to indicate out-of-limit support temperature, voltage, and FANTACH conditions. The - 6 Fan Tachometer Inputs hardware monitoring block of the SCH5027E is acces- - Programmable automatic fan control based sible via the System Management Bus (SMBus). The on temperature same interrupt event reported on the nHWM INT pin - Interrupt Pin for out-of-limit Fantach Events also creates PME wakeup events and speaker alarm - Fantach events generate PMEs annunciation. Temperature Monitor The SCH5027E also allows for a two or three piece lin- - Monitoring of Two Remote Thermal Diodes ear fan function. - Processor temperature monitoring by PECI - Internal Ambient Temperature Measurement The Motherboard Glue logic includes various power - Limit Comparison of all Monitored Values management and system logic including generation of - Interrupt Pin for out-of-limit Temperature Indi- nRSMRST, SMBus buffers, and buffered PCI reset out- cation puts. - Thermal events generate PMEs The SCH5027E incorporates complete legacy Super I/ - Configurable offset for internal or external O functionality including an 8042 based keyboard and temperature channels. mouse controller, an IEEE 1284, EPP, and ECP com- Voltage Monitor patible parallel port, one serial port that is 16C550A - Monitor Power supplies (2 at 1.125V, one at UART compatible, one IrDA 1.0 infrared ports, and a 5V, one each for Vccp, Vbat, VTR, and VCC) floppy disk controller with Microchip s true CMOS 765B - Limit Comparison of all Monitored Values core and enhanced digital data separator, The true - Interrupt Pin for out-of-limit Voltage Indication CMOS 765B core provides 100% compatibility with - Voltage events generate PMEs IBM PC/XT and PC/AT architectures and is software and register compatible with Microchip s proprietary Security Features 82077AA core. System related functionality, which - Security Key Register (32 byte) for Device offers flexibility to the system designer, General Pur- Authentication pose I/O control functions, control of two LED s, and fan 3 VID (Voltage Identification) Inputs control using fan tachometer inputs and pulse width Phoenix Keyboard BIOS ROM modulator (PWM) outputs. 128-Pin QFP, RoHS Compliant Package The SCH5027E is ACPI 1.0/2.0 compatible and there- fore supports multiple low power-down modes. It incor- Description porates sophisticated power control circuitry (PCC), which includes support for keyboard and mouse wake- The SCH5027E is a 3.3V (Super I/O Block is 5V toler- up events. ant) PC99/PC2001 compliant Super I/O controller with an LPC interface. SCH5027E also includes Hardware The SCH5027E supports the ISA Plug-and-Play Stan- Monitoring capabilities, enhanced Security features, dard register set (Version 1.0a). The I/O Address, DMA Power Control logic and Motherboard Glue logic. Channel and hardware IRQ of each logical device in the SCH5027E may be reprogrammed through the The SCH5027E s hardware monitoring capability internal configuration registers. There are up to 480 includes temperature, voltage and fan speed monitor- (960 - Parallel Port) I/O address location options, a ing. It has the ability to alert the system to out-of-limit Serialized IRQ interface, and Three DMA channels. conditions and automatically control the speeds of mul- tiple fans. There are four analog inputs for monitoring external voltages, two at 1.125V, one at 5V and one at 2.25V for Vccp (core processor voltage). There is also internal monitoring of the SIO s VCC, VTR, and Vbat power supplies. The SCH5027E is capable of monitor- ing two external diodes, one internal ambient tempera- ture sensor or retrieving temperatures from external processors that implement the PECI interface. The DS00001784A-page 2 2014 Microchip Technology Inc.