SY100EL14V 5V/3.3V 1:5 Clock Distribution General Description Features The SY100EL14V is a low-skew, 1:5 clock distribution chip 3.3V and 5V power supply options designed explicitly for low-skew clock distribution 70fs typical additive phase jitter RMS applications. The device can be driven by either a Typical 30ps output-to-output skew differential or single-ended ECL or, if positive power Max. 50ps output-to-output skew supplies are used, PECL input signal. The EL14V is suitable for operation in systems operating with 3.3V to Synchronous enable/disable 5.0V supplies. If a single-ended input is to be used, the Multiplexed clock input V output should be connected to the /CLK input and BB 75k internal input pull-down resistors bypassed to ground via a 0.01F capacitor. The V output BB Available in 20-pin SOIC package is designed to act as the switching reference for the input of the EL14V under single-ended input conditions. As a Applications result, this pin can only source/sink up to 0.5mA of current. Processor clock distribution The EL14V features a multiplexed clock input to allow for SONET clock distribution the distribution of a lower speed scan or test clock along Fibre Channel clock distribution with the high speed system clock. When LOW (or left open and pulled LOW by the input pull-down resistor), the SEL Gigabit Ethernet clock distribution pin will select the differential clock input. The common enable (/EN) is synchronous, so that the outputs will only be enabled/disable when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip-flop is clocked on the falling edge of the input clock. Therefore, all associated specification limits are referenced to the negative edge of the clock input. When both differential inputs are left open, CLK input will pull down to V and /CLK input will bias around V /2. EE CC Datasheets and support documentation are available on Micrels web site at: www.micrel.com. Block Diagram Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 Micrel, Inc. SY100EL14V (1) Ordering Information Part Number Package Type Operating Range Package Marking Lead Finish SY100EL14VZG with Pb-Free SY100EL14VZG Z20-1 Industrial Pb-Free bar-line indicator NiPdAu SY100EL14VZG with Pb-Free (2) SY100EL14VZG TR Z20-1 Industrial Pb-Free bar-line indicator NiPdAu Note: 1. Contact factory for die availability. Dice are guaranteed at T = 25C, DC electricals only. A 2. Tape and Reel. Pin Configuration 20-Pin Narrow SOIC (Top View) Pin Description Truth Table Pin Function CLK SCLK SEL /EN Q CLK Differential clock inputs L X L L L SCLK Scan clock input H X L L H /EN Synchronous enable X L H L L SEL Clock select input X H H L H (3) VBB Reference output X X X H L Note: Q0 Q4 Differential clock outputs 3. On next negative transition of CLK or SCLK Revision 5.0 October 16, 2014 2 tcghelp micrel.com or (408) 955-1690