SY100EL15LZG-TR Microchip

ClockWorks Micrel SY100EL15L 3.3V 1:4 CLOCK ClockWorks DISTRIBUTION SY100EL15L Synergy High-Speed Products FEATURES DESCRIPTION The SY100EL15L is a low skew 1:4 clock distribution 3.3V power supply IC designed explicitly for low skew clock distribution 50ps output-to-output skew applications. The device can be driven by either a Low power differential or single-ended ECL or, if positive power Synchronous enable/disable supplies are used, PECL input signal. If a single-ended input is to be used the VBB output should be connected Multiplexed clock input to the CLK input and bypassed to ground via a 0.01 F 75K internal input pull-down resistors capacitor. The VBB output is designed to act as the ESD protection of 2000V switching reference for the input of the EL15 under single- Available in 16-pin SOIC package ended input conditions. As a result, this pin can only source/sink up to 0.5mA of current. The EL15 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or PIN CONFIGURATION/BLOCK DIAGRAM left open and pulled LOW by the input pull-down resistor) the SEL pin will select the differential clock input. CLK CLK VBB EN SCLK SEL VEE The common enable (EN) is synchronous so that the 16 15 14 13 12 11 10 9 outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/ 1 0 disabled as can happen with an asynchronous control. D The internal flip flop is clocked on the falling edge of the Q input clock, therefore all associated specification limits are referenced to the negative edge of the clock input. When both differential inputs are left open, CLK input will pull down to VEE and CLK input will bias around 3 456 7 1 2 8 VCC/2. Q0 Q0 Q1 Q1 Q2 Q3 Q2 SOIC TOP VIEW PIN NAMES TRUTH TABLE Pin Function CLK SCLK SEL EN Q CLK Differential Clock Inputs L X LLL HX L L H SCLK Synchronous Clock Input EN Synchronous Enable XL H L L SEL Clock Select Input XH H L H VBB Reference Output XX X H L* Q0-3 Differential Clock Outputs * On next negative transition of CLK or SCLK Rev.: A Amendment: /0 1999 Micrel Issue Date: December 1999 1 VCC Q3ClockWorks Micrel SY100EL15L (1) ABSOLUTE MAXIMUM RATINGS Symbol Rating Value Unit VEE Power Supply (VCC = 0V) 8.0 to 0 VDC VI Input Voltage (VCC = 0V) 0 to 6.0 VDC IOUT Output Current Continuous 50 mA Surge 100 TA Operating Temperature Range 40 to +85 C NOTES: 1. Absolute maximum rating, beyond which, device life may be impaired, unless otherwise specified on an individual data sheet. 2. Parametric values specified at: 3 volt Power Supply Range 100EL15L Series 3.0V to 3.8V. DC ELECTRICAL CHARACTERISTICS (1) VEE = 3.3V 10% VCC = GND TA = 40CTA = 0CTA = +25CTA = +85C Symbol Parameter Min. Max. Min. Max. Min. Typ. Max. Min. Max. Unit (2) VOH Output HIGH Voltage 1085 880 1025 880 1025 955 880 1025 880 mV (2) VOL Output LOW Voltage 1830 1555 1810 1620 1810 1705 1620 1810 1620 mV (3) VOHA Output HIGH Voltage 1095 1035 1035 1035 mV (3) VOLA Output LOW Voltage 1555 1610 1610 1610 mV VIH Input HIGH Voltage 1165 880 1165 880 1165 880 1165 880 mV VIL Input LOW Voltage 1810 1475 1810 1475 1810 1475 1810 1475 mV IIH Input High Current 150 150 150 150 A (4) IIL Input LOW Current 0.5 0.5 0.5 0.5 A CLK 300 300 300 300 IEE Power Supply Current 35 35 25 35 38 mA VBB Output Reference Voltage 1.38 1.26 1.38 1.26 1.38 1.26 1.38 1.26 V NOTES: 1. This table replaces the three traditionally seen in ECL 100K data books. Outputs are terminated through a 50 resistor to 2.0V. 2. VIN = VIH(Max) or VIL(Min). 3. VIN = VIH(Min) or VIL(Max). 4. VIN = VIL(Max). 2