NOT RECOMMENDED FOR NEW DESIGNS SY10EL34/L SY100EL34/L 5V/3.3V 2, 4, 8 Clock Generation Chip Precision Edge General Description The SY10/100EL34/L are low-skew 2, 4, 8 clock generation chips designed explicitly for low-skew clock Precision Edge generation applications. The internal dividers are Features synchronous to each other therefore, the common output edges are all precisely aligned. The devices can be driven 3.3V and 5V power supply options by either a differential or single-ended ECL or, if positive 50ps output-to-output skew power supplies are used, PECL input signal. In addition, Synchronous enable/disable by using the V output, a sinusoidal source can be AC- BB Master Reset for synchronization coupled into the device. If a single-ended input is to be Internal 75K input pull-down resistors used, the V output should be connected to the CLK BB Available in 16-pin SOIC package input and bypassed to ground via a 0.01F capacitor. The V output is designed to act as the switching reference for BB the input of the EL34/L under single-ended input Pin Description conditions. As a result, this pin can only source/ sink up to Pin Name Pin Function 0.5mA of current. CLK Differential clock inputs. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the Synchronous enable. EN internal clock is already in the LOW state. This avoids any MR Master reset. chance of generating a runt clock pulse on the internal V Reference output. BB clock when the device is enabled/disabled as can happen Q Differential 2 outputs. with an asynchronous control. An internal runt pulse could 0 lead to losing synchronization between the internal divider Q Differential 4 outputs. 1 stages. The internal enable flip-flop is clocked on the Q Differential 8 outputs. 2 falling edge of the divider stages. The internal enable flip- flop is clocked on the falling edge of the input clock therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon start-up, the internal flip-flops will attain a random state the master reset (MR) input allows for the synchronization of the internal dividers, as well as for multiple EL34/Ls in a system. Data sheets and support documentation can be found on Micrels web site at: www.micrel.com. Precision Edge is a registered trademark of Micrel, Inc. Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 Micrel, Inc. Precision Edge SY10EL34/L SY100EL34/L Ordering Information Part Number Package Type Operating Range Package Marking Lead Finish SY10EL34LZG with SY10EL34LZG Z16-2 Industrial Pb-Free NiPdAu Pb-Free Bar Line Indicator (2) SY10EL34LZG with SY10EL34LZGTR Z16-2 Industrial Pb-Free NiPdAu Pb-Free Bar Line Indicator SY100EL34LZG with SY100EL34LZG Z16-2 Industrial Pb-Free NiPdAu Pb-Free Bar Line Indicator SY100EL34LZG with (2) SY100EL34LZGTR Z16-2 Industrial Pb-Free NiPdAu Pb-Free Bar Line Indicator SY10EL34ZG with SY10EL34ZG Z16-2 Industrial Pb-Free NiPdAu Pb-Free Bar Line Indicator SY10EL34ZG with (2) SY10EL34ZGTR Z16-2 Industrial Pb-Free NiPdAu Pb-Free Bar Line Indicator SY100EL34ZG with SY100EL34ZG Z16-2 Industrial Pb-Free NiPdAu Pb-Free Bar Line Indicator SY100EL34ZG with (2) SY100EL34ZGTR Z16-2 Industrial Pb-Free NiPdAu Pb-Free Bar Line Indicator Notes: 1. Contact factory for die availability. Dice are guaranteed at T = 25 C, DC electricals only. A 2. Tape and reel. Pin Configuration 16-Pin Narrow SOIC (Z16-2) M9999-120611-I December 2011 3 hbwhelp micrel.com or (408) 955-1690