SuperLite Micrel, Inc. SY55852U SuperLite D FLIP-FLOP SY55852U FEATURES 2.5GHz min. f MAX SuperLite 2.3V to 5.7V power supply Single bit register memory DESCRIPTION Synchronizes 1 bit of data to a clock Optimized to work with SuperLite family The SY55852U is a flip-flop used to synchronize data Fully differential to a clock. Its differential output will reproduce and remember the value on its input at the rising edge of the Accepts CML, PECL, LVPECL input logic levels clock. In addition, an asynchronous, level sensitive reset Source terminated CML outputs for fast edge rates is provided. For a synchonous reset, the SY55851U Available in a tiny 10-pin MSOP AnyGate can be used. SY55852U inputs can be terminated with a single resistor between the true and complement pins of a given input. The SY55852U is a member of Micrel s SuperLite family of high-speed CML logic. This family features very small packaging and 2.3V to 5.7V operation. FUNCTIONAL BLOCK DIAGRAM APPLICATIONS High-speed logic DATA DQ OUT OC-48 communication systems CLOCK R RESET SuperLite is a trademark of Micrel, Inc. AnyGate is a registered trademark of Micrel, Inc. Rev.: F Amendment: /0 M9999-060407 1 Issue Date: June 2007 hbwhelp micrel.com or (408) 955-1690SuperLite Micrel, Inc. SY55852U PACKAGE/ORDERING INFORMATION (1) Ordering Information VCC /R R Q /Q 10 98 76 Package Operating Package Lead Part Number Type Range Marking Finish SY55852UKC K10-1 Commercial 55852U Sn-Pb Top View MSOP (2) SY55852UKCTR K10-1 Commercial 55852U Sn-Pb SY55852UKI K10-1 Industrial 55852U Sn-Pb 1 23 45 (2) SY55852UKITR K10-1 Industrial 55852U Sn-Pb D /D CLK /CLK GND (3) SY55852UKG K10-1 Industrial 55852U with NiPdAu Pb-Free bar line indicator Pb-Free 10-Pin MSOP (K10-1) (2, 3) SY55852UKGTR K10-1 Industrial 55852U with NiPdAu Pb-Free bar line indicator Pb-Free Notes: 1. Contact factory for die availability. Dice are guaranteed at T = 25C, DC Electricals only. A 2. Tape and Reel. 3. Pb-Free package recommended for new designs. PIN DESCRIPTION Pin Number Pin Name Pin Function 1, 2 D, /D CML/PECL/LVPECL Input (Differential): This is the single bit of data that gets clocked in and remembered. 3, 4 CLK, /CLK CML/PECL/LVPECL Input (Differential): The rising edge of this signal is the clock signal that determines when the Boolean value at the data input gets stored. 5 GND Ground. 6, 7 /Q, Q CML Output (Differential): This is the output of the flip-flop. 8, 9 R, /R CML/PECL/LVPECL Input (Differential): This is an asynchronous active high level reset, that forces the flip-flop into a known state, namely zero. 10 VCC Power Supply. TRUTH TABLE D CLK R Q /Q XX 1 0 1 X0 0 Q /Q N-1 N-1 X1 0 Q /Q N-1 N-1 0 00 1 1 01 0 M9999-060407 2 hbwhelp micrel.com or (408) 955-1690