Precision Edge ULTRA-PRECISION SY58017U Micrel, Inc. Precision Edge DIFFERENTIAL CML 2:1 MUX with SY58017U INTERNAL I/O TERMINATION FEATURES Guaranteed AC performance over temperature and voltage: Precision Edge DC to > 10.7Gbps data throughput DC to > 7GHz f (clock) MAX DESCRIPTION < 240ps propagation delay < 60ps t /t times r f The SY58017U is a 2.5V/3.3V precision, high-speed, 2:1 Ultra-low crosstalk-induced jitter: < 0.7ps rms differential MUX capable of handling clocks up to 7GHz Ultra-low jitter design: and data up to 10.7Gbps. < 1ps random jitter RMS The differential input includes Micrels unique, 3-pin input < 10ps deterministic jitter PP termination architecture that allows customers to interface < 10ps total jitter (clock) PP to any differential signal (AC- or DC-coupled) as small as Unique input termination and V pin accepts DC- T 100mV without any level shifting or termination resistor coupled and AC-coupled inputs (CML, PECL, LVDS) networks in the signal path. The outputs are 50 source Internal 50 output source termination terminated CML, with extremely fast rise/fall times guaranteed to be less than 60ps. Typical 400mV CML output swing (R = 50) L The SY58017U operates from a 2.5V 5% supply or a Power supply 2.5V 5% or 3.3V 10% 3.3V 10% supply and is guaranteed over the full industrial 40C to +85C temperature range temperature range of 40C to +85C. For applications that Available in 16-pin (3mm 3mm) MLF package require LVPECL outputs, consider the SY58018U or SY58019U Multiplexers with LVPECL outputs. The SY58017U is part of Micrels high-speed, Precision Edge APPLICATIONS product line. Redundant clock distribution All support documentation can be found on Micrels web site at www.micrel.com. OC-3 to OC-192 SONET/SDH clock/data distribution Loopback Fibre Channel distribution FUNCTIONAL BLOCK DIAGRAM TYPICAL PERFORMANCE IN0 50 10.7Gbps Output V 0 T0 50 /IN0 Q0 MUX /Q0 IN1 50 S V 1 T1 50 /IN1 SEL (TTL/CMOS) TIME (25ps/div.) 23 (2 1 PRBS) Precision Edge and AnyGate are registered trademarsk of Micrel, Inc. MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc. Rev.: D Amendment: /0 M9999-082807 1 Issue Date: August 2007 hbwhelp micrel.com or (408) 955-1690 Output Swing (100mV/div.) Precision Edge SY58017U Micrel, Inc. PACKAGE/ORDERING INFORMATION (1) Ordering Information Package Operating Package Lead Part Number Type Range Marking Finish 16 15 14 13 SY58017UMI MLF-16 Industrial 017U Sn-Pb IN0 1 12 Q (2) SY58017UMITR MLF-16 Industrial 017U Sn-Pb /IN0 2 11 GND (3) SY58017UMG MLF-16 Industrial 017U with Pb-Free 3 10 GND IN1 Pb-Free bar-line indicator NiPdAu /IN1 4 9 /Q (2, 3) SY58017UMGTR MLF-16 Industrial 017U with Pb-Free 5 6 7 8 Pb-Free bar-line indicator NiPdAu Notes: 1. Contact factory for die availability. Dice are guaranteed at T = 25C, DC electricals only. A 2. Tape and Reel. 16-Pin MLF (MLF-16) 3. Pb-Free package recommended for new designs. PIN DESCRIPTION Pin Number Pin Name Pin Function 1, 2 IN0, /IN0 Differential Input: These input pairs are the differential signal inputs to the device. They 3, 4 IN1, /IN1 accept differential AC- or DC-coupled signals as small as 100mV. Each pin of a pair internally terminates to a V pin through 50 . Note that these inputs will default to an T indeterminate state if left open. Please refer to the Input Interface Applications section for more details. 16, 5 VT0, VT1 Input Termination Center-Tap: Each side of the differential input pair terminates to a V T pin. The V and V pins provide a center-tap to a termination network for maximum T0 T1 interface flexibility. See Input Interface Applications section for more details. 6 SEL This single-ended TTL/CMOS compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25k pull-up resistor and will default to a logic HIGH state if left open. 7NC No connect. 8, 13 VCC Positive Power Supply: Bypass with 0.1F0.01F low ESR capacitors. 0.01F capacitor should be as close to V pin as possible. CC 12, 9 Q, /Q Differential Outputs: This CML output pair is the output of the device. Normally terminate with 100 across Q and /Q. See Output Interface Applications section. It is a logic function of the IN0, IN1, and SEL inputs. Please refer to the Truth Table for details. 10, 11, 14, 15 GND, Ground. Ground pins and exposed pad must be connected to the same ground plane. Exposed Pad TRUTH TABLE TRUTH TABLE SEL Output 0 IN0 Input Selected 1 IN1 Input Selected M9999-082807 2 hbwhelp micrel.com or (408) 955-1690 VT1 VT0 SEL GND NC GND VCC VCC