Precision Edge 5.5GHz 1:4 FANOUT BUFFER/ Micrel, Inc. Precision Edge SY58022U TRANSLATOR w/400mV LVPECL SY58022U OUTPUTS AND INTERNAL INPUT TERMINATION FEATURES Precision 1:4, 400mV LVPECL fanout buffer Precision Edge Guaranteed AC performance over temperature and voltage: DESCRIPTION > 5.5GHz f clock MAX < 80ps t /t times r f The SY58022U is a 2.5V/3.3V precision, high-speed, fully < 250ps (V 300mV) t differential 1:4 LVPECL fanout buffer. Optimized to provide IN pd < 15ps max. skew four identical output copies with less than 15ps of skew and less than 10ps total jitter, the SY58022U can process clock Low jitter performance: PP signals as fast as 5.5GHz. 60fs RMS phase jitter The differential input includes Micrels unique, 3-pin input Accepts an input signal as low as 100mV termination architecture interfaces to differential LVPECL, Unique input termination and V pin accepts T CML, and LVDS signals (AC- or DC-coupled) as small as DC- and AC-coupled differential inputs: LVPECL, 100mV without any level-shifting or termination resistor LVDS and CML networks in the signal path. For AC-coupled input interface 400mV LVPECL compatible outputs applications, an on-board output reference voltage (V ) is REF-AC Power supply 2.5V 5% and 3.3V 10% provided to bias the V pin. The outputs are 400mV LVPECL T compatible, with extremely fast rise/fall times guaranteed to 40C to +85C temperature range be less than 80ps. Available in 16-pin (3mm 3mm) QFN package The SY58022U operates from a 2.5V 5% supply or 3.3V 10% supply and is guaranteed over the full industrial temperature range (40C to +85C). For applications that require greater output swing or CML compatible outputs, consider the SY58021U 1:4 fanout buffer with LVPECL APPLICATIONS outputs, or the SY58020U 1:4 fanout buffer with 400mV CML outputs. The SY58022U is part of Micrels high-speed, All SONET and All GigE clock distribution Precision Edge product line. All data sheets and support Fibre Channel clock and data distribution documentation can be found on Micrels web site at: www. Backplane distribution micrel.com. Data distribution: OC-48, OC-48+FEC, XAUI High-end, low-skew, multiprocessor synchronous clock distribution FUNCTIONAL BLOCK DIAGRAM TYPICAL PERFORMANCE Q0 IN /Q0 50 V T 50 Q1 /IN /Q1 V REF-AC Q2 /Q2 Q3 /Q3 Precison Edge is a registered trademark of Micrel, Inc. Rev.: E Amendment: /1 1 Issue Date: June 2009 Precision Edge Micrel, Inc. SY58022U PACKAGE/ORDERING INFORMATION (1) Ordering Information Package Operating Package Lead 16 15 14 13 Part Number Type Range Marking Finish IN 1 12 Q1 SY58022UMG MLF-16 Industrial 022U with Pb-Free VT 2 11 /Q1 Pb-Free bar-line indicator NiPdAu Q2 VREF-AC 3 10 (2) SY58022UMGTR MLF-16 Industrial 022U with Pb-Free 4 /IN 9 /Q2 Pb-Free bar-line indicator NiPdAu Notes: 5 6 7 8 1. Contact factory for die availability. Die are guaranteed at T = 25C, DC electricals only. A 2. Tape and Reel. 16-Pin QFN PIN DESCRIPTION Pin Number Pin Name Pin Function 1, 4 IN, /IN Differential Input: This input pair receives the signal to be buffered. Each pin is internally terminated with 50 to the V pin. Note that this input will default to an indeterminate state T if left open. See Input Interface Applications section. 2 VT Input Termination Center-Tap: Each input terminates to this pin. The V pin provides a T center-tap for each input (IN, /IN) to the termination network for maximum interface exibility. See Input Interface Applications section. 3 VREF-AC Reference Output Voltage: This output biases to V 1.2V. It is used when AC-coupling CC to differentail inputs. Connect V directly to the V pin. Bypass with 0.01F low ESR REF-AC T capacitor to V . See Input Interface Applications section. CC 8, 13 VCC Positive Power Supply: Bypass with 0.1F//0.01F low ESR capacitors as close to the pins as possible. A 0.01F capacitor should be as close to the V pin as possible. CC 5, 16 GND, Ground. Exposed pad must be connected to a ground plane that is the same potential Exposed Pad as the ground pin. 14, 15 /Q0, Q0, LVPECL Differential Output Pairs: Differential buffered output copy of the input signal. The 11, 12 /Q1, Q1, output swing is typically 400mV. Proper termination is 50 to V 2V at the receiving CC 9, 10 /Q2, Q2, end. Unused output pairs may be left oating with no impact on jitter or skew. 6, 7 /Q3, Q3, See LVPECL Output Termination section. 2 GND GND /Q3 Q0 Q3 /Q0 VCC VCC