SY58020U 6GHz, 1:4 CML Fanout Buffer/Translator with Internal I/O Termination Features General Description Precision 1:4, 400mV CML fanout buffer The SY58020U is a 2.5V/3.3V precision, high-speed, fully Guaranteed AC performance over temperature/voltage: differential 1:4 CML fanout buffer. Optimized to provide four identical output copies with less than 15ps of skew > 6GHz fMAX clock and 27fs of typical additive phase jitter, the SY58020U RMS < 60ps tr / tf times can process clock signals as fast as 6GHz. < 250ps t pd The differential input includes Micrels unique, 3-pin input < 15ps max. skew termination architecture that interfaces to differential Low-jitter performance: LVPECL, LVDS, and CML signals (AC- or DC-coupled) as 27fsRMS typical additive phase jitter small as 100mV without any level-shifting or termination Accepts an input signal as low as 100mV resistor networks in the signal path. For AC-coupled input interface applications, an on-board output reference Unique patented input termination and VT pin accepts voltage (V ) is provided to bias the V pin. The outputs REF-AC T DC-coupled and AC-coupled differential inputs: are optimized to drive 400mV typical swing into 50 loads, LVPECL, LVDS, and CML with extremely fast rise/fall times guaranteed to be less 50 source terminated CML outputs than 60ps. Power supply 2.5V 5% and 3.3V 10% The SY58020U operates from a 2.5V 5% supply or 3.3V Industrial temperature range: 40C to +85C 10% supply and is guaranteed over the full industrial Available in 16-pin (3mm x 3mm) QFN package temperature range (40C to +85C). For applications that require LVPECL outputs, consider the SY58021U or Applications SY58022U 1:4 fanout buffer with 800mV and 400mV All SONET and All GigE clock distribution output swing, respectively. The SY58020U is part of Micrels high-speed, Precision Edge product line. Fibre Channel clock and data distribution Datasheets and support documentation are available on Backplane distribution Micrels web site at: www.micrel.com. Data distribution: OC-48, OC-48+FEC, XAUI High-end, low skew, multiprocessor synchronous clock distribution Functional Block Diagram Typical Performance United States Patent No. RE44,134 Precision Edge is a trademark of Micrel, Inc. Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 Micrel, Inc. SY58020U (1) Ordering Information Part Number Package Type Operating Range Package Marking Lead Finish SY58020UMG QFN-16 Industrial 020U with Pb-Free Pb-Free bar-line indicator NiPdAu (2) SY58020UMG TR QFN-16 Industrial 020U with Pb-Free Pb-Free bar-line indicator NiPdAu Note: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC electrical only. 2. Tape and Reel. Pin Configuration 16-Pin QFN (QFN-16) Pin Description Pin Number Pin Name Pin Function Differential Input: This input pair receives the signal to be buffered. Each pin of this pair internally 1, 4 IN, /IN terminates with 50 to the V pin. Note that this input will default to an indeterminate state if left T open. See Input Interface Applications section. Input Termination Center-Tap: Each input terminates to this pin. The V pin provides a center-tap T 2 VT for each input (IN, /IN) to the termination network for maximum interface flexibility. See Input Interface Applications section. Reference Output Voltage: This output biases to V -1.2V. It is used when AC-coupling to CC 3 VREF-AC differential inputs. Connect V directly to the V pin. Bypass with 0.01F low ESR capacitor REF-AC T to VCC. See Input Interface Applications section. Positive Power Supply: Bypass with 0.1F//0.01F low ESR capacitors as close to the pins as 8, 13 VCC possible. GND, Ground. Exposed pad must be connected to a ground plane that is the same potential as the 5, 16 Exposed Pad ground pin. 14, 15 /Q0, Q0, CML Differential Output Pairs: Differential buffered output copy of the input signal. The output 11, 12 /Q1, Q1, swing is typically 400mV into 50 load. Normally terminate CML output pairs with 100 across Q and /Q outputs at the receiving end. Unused output pairs may be left floating with no impact on 9, 10 /Q2, Q2, jitter or skew. See CML Output Termination section. 6, 7 /Q3, Q3 Revision 5.0 October 27, 2014 2 tcghelp micrel.com or (408) 955-1690