Precision Edge ULTRA PRECISION DIFFERENTIAL SY58029U Micrel, Inc. Precision Edge LVPECL 4:1 MUX with 1:2 FANOUT SY58029U and INTERNAL TERMINATION United States Patent No. RE44,134 FEATURES Selects 1 of 4 differential inputs Precision Edge Provides two copies of the selected input Guaranteed AC performance over temperature and DESCRIPTION voltage: DC-to-> 5Gbps data rate throughput The SY58029U is a 2.5V/3.3V precision, high-speed, 4:1 < 390ps IN-to-Out t pd differential multiplexer with 100k LVPECL (800mV) < 110ps t /t times r f compatible outputs, capable of handling clocks up to 4GHz Ultra low-jitter design: and data streams up to 5Gbps. In addition, a 1:2 fanout < 10ps total jitter (clock) buffer provides two copies of the selected inputs. PP < 1ps random jitter The differential input includes Micrels unique, 3-pin input RMS < 10ps deterministic jitter termination architecture that allows customers to interface PP < 0.7ps crosstalk-induced jitter to any differential signal (AC- or DC-coupled) as small as RMS 100mV without any level shifting or termination resistor Unique patended input design minimizes crosstalk networks in the signal path. The result is a clean, stub-free, Accepts an input signal as low as 100mV low-jitter interface solution. The outputs are 800mV LVPECL, (100k temperature compensated) with extremely fast rise/ Unique patented input termination and V pin T fall times guaranteed to be less than 110ps. accepts DC- and AC-coupled inputs (CML, LVPECL, LVDS) The SY58029U operates from a 2.5V 5% supply or a 3.3V 10% supply and is guaranteed over the full industrial 800mV 100K LVPECL output swing temperature range of 40C to +85C. For applications that Power supply 2.5V 5% or 3.3V 10% require CML outputs, consider the SY58028U. For 400mV LVPECL outputs, consider the SY58030U. The SY58029U 40C to +85C temperature range is part of Micrels high-speed, Precision Edge product line. Available in 32-pin (5mm 5mm) MLF package All support documentation can be found on Micrels web site at www.micrel.com. APPLICATIONS FUNCTIONAL BLOCK DIAGRAM Redundant clock and/or distribution All SONET/SDH clock/data distribution IN0 50 Loopback V T0 All Fibre Channel distribution 50 4:1 /IN0 All Gigabit Ethernet clock and/or data distribution MUX V REF-AC0 1:2 0 Fanout IN1 TYPICAL PERFORMANCE 50 V T1 Q0 50 /Q0 /IN1 1 V REF-AC1 MUX IN2 2 Q1 50 /Q1 V T2 50 /IN2 3 V REF-AC2 IN3 50 V T3 50 /IN3 V REF-AC3 SEL0 (CMOS/TTL) Precision Edge is a registered trademark of Micrel, Inc. SEL1 (CMOS/TTL) MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc. Rev.: D Amendment: /0 M9999-082707 1 Issue Date: August 2007 hbwhelp micrel.com or (408) 955-1690 Precision Edge SY58029U Micrel, Inc. PACKAGE/ORDERING INFORMATION (1) Ordering Information Package Operating Package Lead Part Number Type Range Marking Finish 32 31 30 29 28 27 26 25 SY58029UMI MLF-32 Industrial SY58029U Sn-Pb 1 24 IN0 GND (2) SY58029UMITR MLF-32 Industrial SY58029U Sn-Pb 23 VT0 2 VCC VREF-AC0 3 22 Q1 (3) SY58029UMG MLF-32 Industrial SY58029U with Pb-Free 4 21 /IN0 /Q1 Pb-Free bar-line indicator NiPdAu IN1 5 20 VCC 6 19 VT1 NC (2, 3) SY58029UMGTR MLF-32 Industrial SY58029U with Pb-Free 7 18 VREF-AC1 SEL1 Pb-Free bar-line indicator NiPdAu /IN1 8 VCC 17 910 111213141516 Notes: 1. Contact factory for die availability. Dice are guaranteed at T = 25C, DC electricals only. A 2. Tape and Reel. 3. Pb-Free package recommended for new designs. 32-Pin MLF (MLF-32) PIN DESCRIPTION Pin Number Pin Name Pin Function 1, 4 IN0, /IN0 Differential Input: Each pair accepts AC- or DC-coupled signals as small as 100mV. 5, 8 IN1, /IN1 Each pin of a pair internally terminates to a V pin through 50. Note that these T 25, 28 IN2, /IN2 inputs will default to an indeterminate state if left open. If an input is not used, connect one 29, 32 IN3, /IN3 end of the differential pairs to ground through a 1k resistor, and leave the other end to V through a 825 resistor. Unused V and V pins may also be left floating. CC T REF-AC Please refer to the Input Interface Applications section for more details. 2, 6, 26, 30 VT0, VT1 Input Termination Center-Tap: Each side of the differential input pair terminates to a V T VT2, VT3 pin. The V pin provides a center-tap to the termination network for maximum T interface flexibility. See Input Interface Applications section for more details. 15, 18 SEL0, SEL1 This Single-Ended TTL/CMOS compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25k pull-up resistor and will default to a logic HIGH state if left open. Input logic threshold is V /2. See Truth Table for select control. CC 14, 19 NC No Connect. 10, 13, 16 VCC Positive Power Supply: Bypass with 0.1 F0.01 F low ESR capacitors. 17, 20, 23 11, 12 /Q0, Q0 Differential Outputs: These 100k compatible (internally temperature compensated) 21, 22 /Q1, Q1 LVPECL output pairs are copies of the selected input. Unused output pins may be left floating. See Output Interface for terminating guidelines. 9, 24 GND, Ground. Ground pin and exposed pad must be connected to the same ground plane. Exposed Pad 3, 7, 27, 31 VREF-AC0 Reference Voltage: This reference output is equivalent to V 1.4V. It is used for CC VREF-AC1 AC-coupled inputs. When interfacing to AC input signals, connect V directly to the REF-AC VREF-AC2 V pin and bypass with 0.01F low ESR capacitor to V . See Input Interface Applica- T CC VREF-AC3 tions section. Maximum sink/source current is 0.5mA. TRUTH TABLE SEL1 SEL0 0 0 IN0 Input Selected 0 1 IN1 Input Selected 1 0 IN2 Input Selected 1 1 IN3 Input Selected M9999-082707 2 hbwhelp micrel.com or (408) 955-1690 /IN3 GND VCC VREF-AC3 /Q0 VT3 Q0 IN3 VCC /IN2 NC VREF-AC2 SEL0 VT2 IN2 VCC