Precision Edge ULTRA-PRECISION 1:8 FANOUT SY58032U Micrel, Inc. Precision Edge bUFFER WITH LVPECL OUTPUTS SY58032U AND INTERNAL TERMINATION FEATURES Precision 1:8, LVPECL fanout buffer Guaranteed AC performance over temperature and Precision Edge voltage: DESCRIPTION Clock frequency range: DC to 4GHz <110ps t / t times r f The SY58032U is a 2.5V/3.3V precision, high-speed, <330ps t pd fully differential LVPECL 1:8 fanout buffer. The SY58032U <20ps skew is optimized to provide eight identical output copies with Low-jitter performance: less than 20ps of skew and only 76fs phase jitter. It can RMS 76fs phase jitter (typ) process clock signals as fast as 4GHz. RMS 100k LVPECL compatible outputs The differential input includes Micrels unique, 3-pin input termination architecture that allows the SY58032U to directly Fully differential inputs/outputs interface to LVPECL, CML, and LVDS differential signals Accepts an input signal as low as 100mV (AC- or DC-coupled) without any level-shifting or termination Unique input termination and V pin accepts T resistor networks in the signal path. The result is a clean, DC-coupled and AC-coupled differential inputs: stub-free, low-jitter interface solution. The LVPECL (100k (LVPECL, LVDS, and CML) temperature compensated) outputs feature 800mV typical Power supply 2.5V 5% or 3.3V 10% swing into 50 loads, and provide an extremely fast rise/fall time guaranteed to be less than 110ps. Industrial temperature range: 40C to +85C The SY58032U operates from a 2.5V 5% supply or Available in 32-pin (5mm x 5mm) MLF package 3.3V 10% supply and is guaranteed over the full industrial temperature range (40C to +85C). For applications that require a higher high-speed 1:8 fanout buffer, consider the SY58031U or SY58033U. The SY58032U is part of Micrels high-speed, Precision Edge product line. All support documentation can be found on Micrels web site at www.micrel.com. APPLICATIONS FUNCTIONAL bLOCk DIAGRAM All SONET and all GigE clock distribution Q0 All Fibre Channel clock and data distribution /Q0 Network routing engine timing distribution Q1 High-end, low-skew multiprocessor synchronous /Q1 clock distribution Q2 /Q2 IN 50 Q3 V T /Q3 50 /IN Q4 /Q4 V REF-AC Q5 /Q5 Q6 /Q6 Q7 United States Patent No. RE44,134 /Q7 Precision Edge is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc. Rev.: E Amendment: /0 M9999-072810 1 Issue Date: July 2010 hbwhelp micrel.com or (408) 955-1690 Precision Edge SY58032U Micrel, Inc. PACkAGE/ORDERING INFORMATION (1) Ordering Information Package Operating Package Lead 32 31 30 29 28 27 26 25 Part Number Type Range Marking Finish 1 24 GND VCC SY58032UMI MLF-32 Industrial SY58032U Sn-Pb 23 GND 2 VCC (2) IN 3 22 Q3 SY58032UMITR MLF-32 Industrial SY58032U Sn-Pb 4 21 VT /Q3 (3) SY58032UMG MLF-32 Industrial SY58032U with Pb-Free 5 20 VREF-AC Q4 /IN 6 19 /Q4 Pb-Free bar-line indicator NiPdAu 7 GND 18 VCC (2, 3) SY58032UMGTR MLF-32 Industrial SY58032U with Pb-Free VCC 8 17 GND 9 10 11 12 13 14 15 16 Pb-Free bar-line indicator NiPdAu Notes: 1. Contact factory for die availability. Dice are guaranteed at T = 25C, DC electricals only. A 2. Tape and Reel. 32-Pin MLF (MLF-32) 3. Pb-Free package recommended for new designs. PIN DESCRIPTION Pin Number Pin Name Pin Function 3, 6 IN, /IN Differential Signal Input: Each pin of this pair internally terminates with 50 to the V T pin. Note that this input will default to an indeterminate state if left open. See Input Interface Applications section. 4 VT Input Termination Center-Tap: Each input terminates to this pin. The V pin provides a T center-tap for each input (IN, /IN) to the termination network for maximum interface flexibility. See Input Interface Applications section. 2, 7, 17, 24 GND, Ground. Exposed pad must be connected to a ground plane that is the same potential Exposed Pad as the ground pin. 1, 8, 9, 16, VCC Positive Power Supply: Bypass with 0.1F 0.01F low ESR capacitors as close to the 18, 23, 25, 32 pins as possible. 31, 30, 29, 28, 27, Q0, /Q0, Q1, /Q1, 100k LVPECL Differential Output Pairs: Differential buffered output copy of the 26, 22, 21, 20, 19, Q2, /Q2, Q3, /Q3, input signal. The LVPECL output swing is typically 800mV into 50. Unused output 15, 14, 13, 12, Q4, /Q4, Q5, /Q5, pairs may be left floating with no impact on jitter. See LVPECL Output section. 11, 10 Q6, /Q6, Q7, /Q7 5 VREF-AC Bias Reference Voltage: Equal to V 1.2V (typical), and used for AC-coupled CC applications. See Input Interface Applications section. When using V , bypass REF-AC with 0.01F capacitor to V . Maximum sink/source current is 0.5mA. CC M9999-072810 2 hbwhelp micrel.com or (408) 955-1690 VCC VCC /Q7 Q0 Q7 /Q0 /Q6 Q1 Q6 /Q1 /Q5 Q2 Q5 /Q2 VCC VCC