Precision Edge 4.5GHz, 1:6 LVPECL FANOUT SY58035U Micrel, Inc. Precision Edge BUFFER WITH 2:1 MUX INPUT SY58035U AND INTERNAL TERMINATION FEATURES Provides six ultra-low skew copies of the selected input Precision Edge 2:1 MUX input included for clock switchover applications DESCRIPTION Guaranteed AC performance over temperature and voltage: The SY58035U is a 2.5V/3.3V precision, high-speed, 1:6 Clock frequency range: DC to > 4.5GHz fanout capable of handling clocks up to 4.5GHz. A differential <320ps IN-to-OUT t pd 2:1 MUX input is included for redundant clock switchover <110ps t / t times r f applications. <20ps skew (output-to-output) The differential input includes Micrels unique, 3-pin input Ultra-low jitter design: termination architecture that allows the device to interface 50fs phase jitter (typ) RMS to any differential signal (AC- or DC-coupled) as small as Low supply voltage operation: 2.5V and 3.3V 100mV without any level shifting or termination resistor networks in the signal path. The outputs are LVPECL (100K, Unique input termination and VT pin accepts DC- temperature compensated), with extremely fast rise/fall times coupled and AC-coupled inputs (CML, PECL, LVDS) guaranteed to be less than 110ps. Unique input isolation design minimizes crosstalk The SY58035U operates from a 2.5V 5% supply or a 100K LVPECL compatible output swing 3.3V 10% supply and is guaranteed over the full industrial 40C to +85C temperature range temperature range of 40C to +85C. For applications that Available in 32-pin (5mm x 5mm) MLF package require CML outputs, consider the SY58034U or for 400mV LVPECL outputs the SY58036U. The SY58035U is part of Micrels high-speed, Precision Edge product line. All support documentation can be found on Micrels web site at www.micrel.com. APPLICATIONS FUNCTIONAL BLOCK DIAGRAM Redundant clock distribution 1:6 Fanout All SONET/SDH clock/data distribution Q0 All Fibre Channel distribution /Q0 All Gigabit Ethernet clock distribution 2:1 Mux IN0 Q1 50 /Q1 V 0 T0 50 /IN0 Q2 V REF-AC0 Mux /Q2 IN1 50 Q3 1 S V T1 /Q3 50 /IN1 Q4 V REF-AC1 /Q4 SEL (TTL/CMOS) Q5 /Q5 United States Patent No. RE44,134 Precision Edge is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc. Rev.: F Amendment: /0 M9999-073010 1 Issue Date: July 2010 hbwhelp micrel.com or (408) 955-1690 Precision Edge SY58035U Micrel, Inc. PACKAGE/ORDERING INFORMATION (1) Ordering Information Package Operating Package Lead Part Number Type Range Marking Finish 32 31 30 29 28 27 26 25 IN0 1 24 GND SY58035UMI MLF-32 Industrial SY58035U Sn-Pb 23 VT0 2 VCC (2) SY58035UMITR MLF-32 Industrial SY58035U Sn-Pb VREF-AC0 3 22 Q2 4 21 /IN0 /Q2 (3) SY58035UMG MLF-32 Industrial SY58035U with NiPdAu 5 20 IN1 Q3 Pb-Free bar-line indicator Pb-Free VT1 6 19 /Q3 (2, 3) 7 18 VREF-AC1 VCC SY58035UMGTR MLF-32 Industrial SY58035U with NiPdAu /IN1 8 17 GND Pb-Free bar-line indicator Pb-Free 9 10 11 12 13 14 15 16 Notes: 1. Contact factory for die availability. Dice are guaranteed at T = 25C, DC electricals only. A 2. Tape and Reel. 32-Pin MLF (MLF-32) 3. Pb-Free package recommended for new designs. PIN DESCRIPTION Pin Number Pin Name Pin Function 1, 4 IN0, /IN0 Differential Input: These input pairs are the differential signal inputs to the device. These 5, 8 IN1, /IN1 inputs accept AC- or DC-coupled signals as small as 100mV. Each pin of a pair internally terminates to a VT pin through 50. Note that these inputs will default to an indeterminate state if left open. Please refer to the Input Interface Applications section for more details. 2, 6 VT0, VT1 Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VT0 and VT1 pins provide a center-tap to a termination network for maximum interface flexibility. See Input Interface Applications section for more details. 31 SEL This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25k pull-up resistor and will default to a logic HIGH state if left open. The MUX select switchover function is asynchronous. 10 NC No connect. 11, 16, 18, VCC Positive Power Supply: Bypass with 0.1F 0.01F low ESR capacitors and place as 23, 25, 30 close to the VCC pin as possible. 29, 28 Q0, /Q0, Differential Outputs: These 100K (temperature compensated) LVPECL output pairs are 27, 26 Q1, /Q1, low skew copies of the selected input. Please refer to the Truth Table for details. 22, 21 Q2, /Q2, 20, 19 Q3, /Q3, 15, 14 Q4, /Q4, 13, 12 Q5, /Q5 9, 17, 24, 32 GND, Ground: Ground pin and exposed pad must be connected to the same ground plane. Exposed Pad 3, 7 VREF-AC0 Reference Voltage: These output biases to V 1.2V. It is used for AC-coupling inputs CC VREF-AC1 (IN, /IN). Connect V directly to the VT pin. Bypass with 0.01F low ESR capacitor to REF-AC V . See Input Interface Applications section. Maximum sink/source current is 1.5mA. CC Due to the limited drive capability, the VREF-AC pin is only intended to drive its respective VT pin. TRUTH TABLE SEL 0 IN0 Input Selected 1 IN1 Input Selected M9999-073010 2 hbwhelp micrel.com or (408) 955-1690 GND GND NC SEL VCC VCC /Q5 Q0 Q5 /Q0 /Q4 Q1 Q4 /Q1 VCC VCC