Precision Edge 3.3V 1GHz PRECISION 1:22 LVDS Micrel, Inc. SY89826L Precision Edge FANOUT BUFFER/TRANSLATOR SY89826L WITH 2:1 INPUT MUX FEATURES High-performance, 1GHz LVDS fanout buffer/ Precision Edge translator 22 differential LVDS output pairs DESCRIPTION Guaranteed AC parameters over temperature and voltage: The SY89826L is a precision fanout buffer with 22 > 1GHz f MAX differential LVDS (Low Voltage Differential Swing) output < 50ps within device skew pairs. The part is designed for use in low voltage 3.3V < 400ps t /t time r f applications that require a large number of outputs to drive Low jitter performance precisely aligned, ultra low-skew signals to their destination. < 1ps (rms) cycle-to-cycle jitter The input is multiplexed from either LVDS or LVPECL (Low < 1ps (pk-pk) total jitter Voltage Positive Emitter Coupled Logic) by the CLK SEL 2:1 mux input accepts LVDS and LVPECL pin. The OE (Output Enable) is synchronous so that the 3.3V supply voltage outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a LVDS input includes internal 100 termination runt clock pulse when the device is enabled/disabled as Output enable function can happen with an asynchronous control. Available in a 64-Pin EPAD-TQFP The SY89826L features a low pin-to-pin skew of less than 50psperformance previously unachievable in a standard product having such a high number of outputs. APPLICATIONS The SY89826L is available in a single space saving package, enabling a lower overall cost solution. Enterprise networking High-end servers Communications TRUTH TABLE FUNCTIONAL BLOCK DIAGRAM (1) OE CLK SEL Q0 Q21 /Q0 /Q21 100 internal input termination 0 0 LOW HIGH 22 LVDS compatible CLK SEL 0 1 LOW HIGH outputs LVDS CLK 1 0 LVDS CLK /LVDS CLK 0 /LVDS CLK 1 1 LVPECL CLK /LVPECL CLK 22 Q0 - Q21 NOTE: 22 /Q0 - /Q21 1. The OE (output enable) signal is synchronized with the low level of the LVDS CLK and LVPECL CLK signal. LVPECL CLK 1 LEN Q /LVPECL CLK OE D Precision Edge is a registered trademark of Micrel, Inc. Rev.: D Amendment: /0 M9999-011907 11 Issue Date: January 2007 hbwhelp micrel.com or (408) 955-1690 Precision Edge Micrel, Inc. SY89826L PACKAGE/ORDERING INFORMATION (1) Ordering Information 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Package Operating Package Lead VCCO 1 48 GNDO GNDO 2 47 Q7 Part Number Type Range Marking Finish 46 /Q7 NC 3 45 Q8 VCCI 4 SY89826LHI H64-1 Industrial SY89826LHI Sn-Pb 44 /Q8 LVDS CLK 5 43 Q9 /LVDS CLK 6 (2) 42 /Q9 CLK SEL 7 SY89826LHITR H64-1 Industrial SY89826LHI Sn-Pb LVPECL CLK 41 Q10 8 /LVPECL CLK 40 /Q10 9 (3) SY89826LHY H64-1 Industrial SY89826LHY with Pb-Free GNDI 39 Q11 10 38 /Q11 OE 11 Pb-Free bar-line indicator Matte-Sn 37 Q12 NC 12 36 /Q12 GNDO 13 (2, 3) /Q21 35 Q13 14 SY89826LHYTR H64-1 Industrial SY89826LHY with Pb-Free Q21 34 /Q13 15 33 VCCO 16 GNDO Pb-Free bar-line indicator Matte-Sn 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Notes: 1. Contact factory for die availability. Dice are guaranteed at T = 25C, DC electricals only. A 2. Tape and Reel. 64-Pin TQFP (H64-1) 3. Pb-Free package recommended for new designs. PIN DESCRIPTIONS Internal Pull-up/ Pull-down Pin Number Pin Name I/O Type Pin Function 5, 6 LVDS CLK Input LVDS 3.3k Differential LVDS clock input. Selected when CLKSEL = LOW /LVDS CLK w/100 pull-up (Can be left floating if CLKSEL = HIGH). This input pair internal (Figure 2) includes internal termination, and is intended to interface terminator directly to LVDS. Leave floating if not used. 8, 9 LVPECL CLK Input LVPECL 75k Differential LVPECL clock input. Selected when CLKSEL = /LVPECL CLK pull-down HIGH (Can be left floating if CLKSEL = LOW). Requires (Figure 1) external termination. Leave floating if not used. 7 CLK SEL Input LVTTL/ 11k to Selects LVDS CLK when LOW and LVPECL CLK when CMOS VCCI HIGH. Default condition is HIGH if left floating. 11 OE Input LVTTL/ Output enable/disable function. When LOW, Q outputs go LOW, /Q outputs go HIGH. Asynchronous input that is synchronized internally to prevent output glitches or runt pulses. 63, 61, 59, 57, 55, 53, Q0 Q21 Output LVDS Differential LVDS clock outputs when OE = HIGH and static 51, 47, 45, 43, 41, 39, LOW when OE = LOW. Unused output pairs must be 37, 35, 31, 29, 27, 25, terminated with 100 across the differential pair to maintain 23, 21, 19, 15 low skew and jitter. 62, 60, 58, 56, 54, 52, /Q0 /Q21 Output LVDS Differential clock outputs (complement) when OE = HIGH 50, 46, 44, 42, 40, 38, and static HIGH when OE = LOW. Unused output pairs 36, 34, 30, 28, 26, 24, must be terminated with 100 across the differential pair to 22, 20, 18, 14 maintain low skew and jitter. 4 VCCI Power Core VCC connect to 3.3V supply. Not connected to VCCO internally. Connect to VCCO on PCB. Bypass with 0.1 F in parallel with 0.01 F low ESR capacitors as close to VCC pins as possible. 1, 16, 17, VCCO Power Output buffer VCC connects to 3.3V supply. Not connected 32, 49, 64 to VCCI internally. Connect to VCCI on PCB. Bypass with 0.1 F in parallel with 0.01 F low ESR capacitors as close to VCC pins as possible. 10 GNDI Power Core ground not connected to GNDO internally. Connect to GNDO on PCB. 2, 13, 33, 48 GNDO Power Output buffer ground not connected to GNDI internally. Connect to GNDI on PCB. 3, 12 NC No connect pins to be left open. M9999-011907 2 hbwhelp micrel.com or (408) 955-1690 VCCO VCCO /Q20 Q0 Q20 /Q0 /Q19 Q1 Q19 /Q1 /Q18 Q2 /Q2 Q18 Q3 /Q17 /Q3 Q17 Q4 /Q16 /Q4 Q16 Q5 /Q15 /Q5 Q15 Q6 /Q14 Q14 /Q6 VCCO VCCO