Precision Edge 2.5V/3.3/5V 2.5GHz 1:4 PECL/ECL Micrel, Inc. SY89830U Precision Edge CLOCK DRIVER WITH 2:1 SY89830U DIFFERENTIAL INPUT MUX FEATURES Guaranteed AC parameters over temp/voltage: Precision Edge > 2.5GHz f MAX < 25ps within-device skew < 225ps t /t time r f DESCRIPTION < 450ps prop delay Low jitter design: The SY89830U is a high-speed, 2.5GHz differential PECL 1:4 fanout buffer optimized for ultra-low skew applications. < 1ps cycle-to-cycle jitter RMS Within device skew is guaranteed to be less than 25ps over < 15ps total jitter PP temperature and supply voltage. The wide supply voltage 2:1 Differential MUX input operation allows this fanout buffer to operate in 2.5V, 3.3V, Flexible supply voltage: 2.5V/3.3V/5V and 5V systems. Wide operating temperature range: 40C to +85C The SY89830U features a 2:1 input MUX, making it an ideal solution for redundant clock switchover applications. 100K ECL compatible outputs If only one input pair is used, the other pair may be left Inputs accept PECL/LVPECL/ECL/HSTL logic levels floating. In addition, this device includes a synchronous Available in a 16-pin TSSOP package enable pin that forces the outputs into a fixed logic state. Enable or disable state is initiated only after the outputs are in a LOW state, thus eliminating the possibility of a runt clock pulse. The SY89830U I/O are fully differential and 100K ECL compatible. Differential 10K ECL logic can interface directly into the SY89830U inputs. The SY89830U is part of Micrels high-speed precision edge timing and distribution family. For applications that require a different I/O combination, consult the Micrel website at www.micrel.com, and choose from a comprehensive product line of high-speed, low-skew fanout buffers, translators, and clock generators. Precision Edge is a registered trademark of Micrel, Inc. Rev.: E Amendment: /0 M9999-110705 1 hbwhelp micrel.com or (408) 955-1690 Issue Date: November 2005 Precision Edge Micrel, Inc. SY89830U PACKAGE/ORDERING INFORMATION (1) Ordering Information Q0 16 VCC 1 Package Operating Package Lead Part Number Type Range Marking Finish /EN 2 15 /Q0 D Q SY89830UK4I K4-16-1 Industrial 89830U Sn-Pb Q1 /IN1 3 14 (2) SY89830UK4ITR K4-16-1 Industrial 89830U Sn-Pb (3) SY89830UK4G K4-16-1 Industrial 89830U with NiPdAu /Q1 4 13 IN1 1 Pb-Free bar line indicator Pb-Free Q2 12 /IN0 5 (2, 3) SY89830UK4GTR K4-16-1 Industrial 89830U with NiPdAu 0 Pb-Free bar line indicator Pb-Free /Q2 IN0 6 11 Notes: Q3 IN SEL 7 10 1. Contact factory for die availability. Dice are guaranteed at T = 25C, DC Electricals only. A 2. Tape and Reel. /Q3 8 9 VEE 3. Pb-Free package is recommended for new designs. 16-Pin TSSOP (T32-1) PIN DESCRIPTION Pin Number Pin Name Pin Function 1, 2, 3, 4, Q0 to Q3 (LV)PECL, (LV)ECL differential outputs: Terminate with 50 to V 2V. For CC 5, 6, 7, 8 /Q0 to /Q3 single-ended applications, terminate the unused output with 50 to V 2V. CC 9V Negative Power Supply: For LVPECL, PECL applications, connect to GND. EE 10 IN SEL (LV)PECL, (LV)ECL compatible 2:1 mux input signal select: When IN SEL is LOW, the IN0 input pair is selected. When IN SEL is HIGH, the IN1 input pair is selected. Includes a 75k pull-down. Default state is LOW and IN0 is selected. 11, 12, 13, 14 IN0, /IN0 (LV)PECL, (LV)ECL, HSTL clock or data inputs. IN1, /IN1 Internal 75k pull-down resistors on IN0, IN1. Internal 75k pull-up and 75k pull-down resistors on /IN0, /IN1. /IN0, /IN1 default condition is V /2 when left floating. IN0, IN1 default condition is LOW CC when left floating. 15 /EN (LV)PECL, (LV)ECL compatible synchronous enable: When /EN goes HIGH, Q will OUT go LOW and /Q will go HIGH on the next LOW input clock transition. Includes a 75k OUT pull-down. Default state is LOW when left floating. The internal latch is clocked on the falling edge of the input (IN0, IN1) 16 V Positive Power Supply: Bypass with 0.1 F//0.01 F low ESR capacitors. CC (1) TRUTH TABLE IN0 IN1 IN SEL /EN Q LX L L L HX L L H XL H L L XH H L H XL H L XHHL Note: 1. = negative edge M9999-110705 2 hbwhelp micrel.com or (408) 955-1690