SY89847U 1.5 GHz Precision LVDS 1:5 Fanout with 2:1 MUX and Fail Safe Input with Internal Termination Features General Description Selects Between Two Sources and Provides 5 The SY89847U is a 2.5V, 1:5 LVDS fanout buffer with a Precision LVDS Copies 2:1 differential input multiplexer (MUX). A unique fail safe input (FSI) protection prevents metastable output Fail Safe Input Prevents Outputs from Oscillating conditions when the selected input clock fails to a DC when Input is Invalid voltage (voltage between the pins of the differential Guaranteed AC Performance over Temperature input drops significantly below 100 mV). and Supply Voltage: The differential input includes Microchips unique, 3-pin - DC-to >1.5 GHz Throughput internal termination architecture that can interface to - <1000 ps Propagation Delay (IN-to-Q) any differential signal (AC- or DC-coupled) as small as - <210 ps Rise/Fall Times 100mV (200mV ) without any level shifting or PP Ultra-Low Jitter Design: termination resistor networks in the signal path. The -<1ps Random Jitter outputs are LVDS compatible with very fast rise/fall RMS -<1ps Cycle-to-Cycle Jitter times guaranteed to be less than 210 ps. RMS Total Jitter (Clock) -<10ps The SY89847U operates from a 2.5V 5% supply and PP is guaranteed over the full industrial temperature range -<0.7ps MUX Crosstalk Induced Jitter RMS of 40C to +85C. The SY89847U is part of Unique, Patented MUX Input Isolation Design Microchips high-speed, Precision Edge product line. Minimizes Adjacent Channel Crosstalk Unique, Patented Internal Termination and V Pin T Accepts DC- and AC-Coupled Inputs (CML, PECL, LVDS) Package Type Wide Input Voltage Range V to GND SY89847U CC 2.5V 5% Supply Voltage 5 mm x 5 mm QFN-32 (M) (Top View) 40C to +85C Industrial Temperature Range Available in 32-Pin (5 mm x 5 mm) QFN Package Applications Fail Safe Clock Protection Ultra-Low Jitter LVDS Clock Distribution 32 31 30 29 28 27 26 25 Rack-Based Telecom/Datacom 1 24 VT0 Q1 2 23 IN0 /Q1 Markets /IN0 3 22 VCC LAN/WAN 4 21 OE Q2 Enterprise Servers 5 20 SEL /Q2 ATE 6 19 IN1 VCC Test and Measurement 7 18 /IN1 Q3 8 17 VT1 /Q3 910 11 12 13 14 15 16 United States Patent Nos. RE44,134 and 7,123,074 2018 Microchip Technology Inc. DS20006101A-page 1 VREF-AC1 VREF-AC0 GND GND GND GND VCC VCC VCC VCC /Q4 Q0 Q4 /Q0 VCC VCCSY89847U Functional Block Diagram Q0 /Q0 IN0 Q1 SEL V /Q1 T0 0 Q2 /IN0 V REF-AC0 /Q2 IN1 Q3 1 V T1 /Q3 Enable /IN1 Logic Q4 V REF-AC1 OE /Q4 DS20006101A-page 2 2018 Microchip Technology Inc.