Precision Edge 3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS Micrel, Inc. SY89873L Precision Edge PROGRAMMABLE CLOCK DIVIDER SY89873L FANOUT BUFFER W/ INTERNAL TERMINATION FEATURES Guaranteed AC performance Precision Edge > 2.0GHz f output toggle MAX > 3.0GHz f input MAX DESCRIPTION < 800ps t (matched-delay between banks) PD < 15ps within-device skew This 3.3V low-skew, low-jitter, precision LVDS output clock < 190ps rise/fall time divider accepts any high-speed differential clock input (AC- or Low jitter design DC-coupled) CML, LVPECL, HSTL or LVDS and divides down < 1ps cycle-to-cycle jitter RMS the frequency using a programmable divider ratio to create a frequency-locked, lower speed version of the input clock. The Unique input termination and V pin for DC-coupled T SY89873L includes two output banks. Bank A is an exact and AC-coupled inputs: any differential inputs copy of the input clock (pass through) with matched (LVPECL, LVDS, CML, HSTL) propagation delay to Bank B, the divided output bank. Available Precision differential LVDS outputs divider ratios are 2, 4, 8 and 16. In a typical 622MHz clock system this would provide availability of 311MHz, 155MHz, Matched delay: all outputs have matched delay, 77MHz or 38MHz auxiliary clock components. independent of divider setting The differential input buffer has a unique internal termination TTL/CMOS inputs for select and reset/disable design that allows access to the termination network through Two LVDS output banks (matched delay) a VT pin. This feature allows the device to easily interface to Bank A: Buffered copy of input clock (undivided) all AC- or DC-coupled differential logic standards. A V REF-AC Bank B: Divided output (2, 4, 8, 16), reference is included for AC-coupled applications. two copies The SY89873L is part of Micrels high-speed Precision 3.3V power supply Edge timing and distribution family. For 2.5V applications, consider the SY89872U. For applications that require an Wide operating temperature range: 40 C to +85 C LVPECL output, consider the SY89871U. Available in 16-pin (3mm 3mm) QFN package The /RESET input asynchronously resets the divider outputs (Bank B). In the pass-through function (Bank A) the /RESET APPLICATIONS synchronously enables or disables the outputs on the next falling edge of IN (rising edge of /N). Refer to the Timing SONET/SDH line cards Diagram. Transponders All support documentation can be found on Micrels web High-end, multiprocessor servers site at: www.micrel.com. FUNCTIONAL BLOCK DIAGRAM TYPICAL APPLICATION Enable /RESET 622MHz/155.5MHz FF SONET Clock Generator Enable QA MUX V REF-AC QA 622MHz LVDS /QA /QA Clock Out OC-12 or 622MHz LVPECL IN IN OC-3 Clock In /IN 50 QB0 Clock Gen QB 155.5MHz LVDS V T Divided 50 /QB0 /QB Clock Out by /IN 2, 4, 8 QB1 or 16 Bank B: 155.5MHz: For OC-3 line card /QB1 Set to divide-by-4 Bank A: 622MHz: For OC-12 line card S0 Set to pass-through Decoder S1 Precision Edge is a registered trademark of Micrel, Inc. Rev.: F Amendment: /0 M9999-082407 1 Issue Date: February 2007 hbwhelp micrel.com or (408) 955-1690 Precision Edge Micrel, Inc. SY89873L PACKAGE/ORDERING INFORMATION (1) Ordering Information Package Operating Package Lead 16 15 14 13 Part Number Type Range Marking Finish QB0 1 12 IN SY89873LMG QFN-16 Industrial 873L with NiPdAu /QB0 2 VT 11 Pb-Free bar line indicator Pb-Free VREF-AC QB1 3 10 (2) SY89873LMGTR QFN-16 Industrial 873L with NiPdAu 4 /QB1 9 /IN Pb-Free bar line indicator Pb-Free 5 6 7 8 Notes: 1. Contact factory for die availability. Dice are guaranteed at T = 25C, DC Electricals only. A 2. Tape and Reel. 16-Pin QFN PIN DESCRIPTION Pin Number Pin Name Pin Function 1, 2, 3, 4 QB0, /QB0 Differential Buffered Output Clocks: Divide by 2, 4, 8, 16. QB1, /QB1 LVDS compatible. 5, 6 QA, /QA Differential Buffered Undivided Output Clock: LVDS compatible. 7, 14 VCC Positive Power Supply: Bypass with 0.1 F//0.01F low ESR capacitors. 8 /RESET, TTL/CMOS Compatible Output Reset and Disable: Internal 25k pull-up. Input threshold /DISABLE is V /2. Logic LOW will reset the divider select, and align Bank A and Bank B edges. In CC addition, when LOW, Banks A and B will be disabled. 12, 9 IN, /IN Differential Input: Internal 50 termination resistors to V input. T See Input Interface Applications section. 10 VREF-AC Reference Voltage: Equal to V 1.4V (approx.), and used for AC-coupled applications. CC Maximum sink/source current is 0.5mA. See Input Interface Applications section. 11 VT Termination Center-Tap: For CML and LVDS inputs, leave this pin floating. Otherwise, see Input Interface Applications section. 13 GND Ground: Exposed pad is internally connected to GND and must be connected to a ground plane for proper thermal operation. 16, 15 S0, S1 Select Pins: LVTTL/CMOS logic levels. Internal 25k pull-up resistor. Logic HIGH if left unconnected (divided by 16 mode). S0 = LSB. Input threshold is V /2. CC TRUTH TABLE /RESET S1 S0 Bank A Output Bank B Outputs /DISABLE 1 0 0 Input Clock Input Clock 2 1 0 1 Input Clock Input Clock 4 1 1 0 Input Clock Input Clock 8 1 1 1 Input Clock Input Clock 16 (1) (2) 0 X X QA = LOW, /QA = HIGH QB0 = LOW, /QB0 = HIGH (2) QB1 = LOW, /QB1 = HIGH Notes: 1. On the next negative transition of the input signal. 2. Asynchronous Reset/Disable function. SeeTiming Diagram M9999-082407 2 hbwhelp micrel.com or (408) 955-1690 QA S0 /QA S1 VCC VCC /RESET GND /DISABLE