Precision Edge 3.3V, 2.0GHz ANY DIFFERENTIAL IN-TO-LVDS Micrel, Inc. SY89876L Precision Edge PROGRAMMABLE CLOCK DIVIDER AND SY89876L 1:2 FANOUT BUFFER W/ INTERNAL TERMINATION FEATURES DESCRIPTION Integrated programmable clock divider and 1:2 This low-skew, low-jitter device is capable of accepting a fanout buffer high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal and dividing down the frequency Guaranteed AC performance over temperature and using a programmable divider ratio to create a lower speed voltage: version of the input clock. Available divider ratios are 2, 4, 8 >2.0GHz f MAX and 16, or straight pass-through. <190ps t /t r f <15ps within device skew The differential input buffer has a unique internal termination design that allows access to the termination Low jitter design: network through a VT pin. This feature allows the device to <10ps total jitter PP easily interface to different logic standards. A V <1ps cycle-to-cycle jitter REF-AC RMS reference is included for AC-coupled applications. Unique input termination and VT Pin for DC- and AC- The /RESET input asynchronously resets the divider. In coupled inputs CML, PECL, LVDS and HSTL the pass-through function (divide by 1) the /RESET LVDS-compatible outputs synchronously enables or disables the outputs on the next TTL/CMOS inputs for select and reset falling edge of IN (rising edge of /IN). Parallel programming capability Programmable divider ratios of 1, 2, 4, 8 and 16 Low voltage operation 3.3V Output disable function 40C to 85C industrial temperature range Available in 16-pin (3mm x 3mm) MLF package TYPICAL PERFORMANCE APPLICATIONS SONET/SDH line cards OC-12 to OC-3 Translator/Divider Transponders High-end, multiprocessor servers CML/LVPECL/LVDS LVDS Divide-by-4 622MHz 155.5MHz FUNCTIONAL BLOCK DIAGRAM Clock In Clock Out S2 (TTL/CMOS) /RESET 622MHz In Enable (TTL/CMOS) FF IN Enable Q0 MUX /Q0 MUX /IN Q1 IN Divided 50 /Q1 by 155.5MHz Out V T Q0 2, 4, 8 50 or 16 /IN S1 (TTL/CMOS) Decoder S0 (TTL/CMOS) /Q0 V REF AC United States Patent No. RE44,134 Precision Edge is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc. Rev.: E Amendment: /0 M9999-082407 11 Issue Date: August 2007 hbwhelp micrel.com or (408) 955-1690 Precision Edge Micrel, Inc. SY89876L PACKAGE/ORDERING INFORMATION (1) Ordering Information Package Operating Package Lead 16 15 14 13 Part Number Type Range Marking Finish 1 12 IN Q0 SY89876LMI MLF-16 Industrial 876L Sn-Pb /Q0 2 11 VT (2) SY89876LMITR MLF-16 Industrial 876L Sn-Pb 3 10 VREF-AC Q1 (3) SY89876LMG MLF-16 Industrial 876L with Pb-Free /Q1 4 9 /IN Pb-Free bar-line indicator NiPdAu (2, 3) 5 6 7 8 SY89876LMGTR MLF-16 Industrial 876L with Pb-Free Pb-Free bar-line indicator NiPdAu Notes: 1. Contact factory for die availability. Dice are guaranteed at T = 25C, DC Electricals only. A 2. Tape and Reel. 16-Pin MLF (MLF-16) 3. Pb-Free package is recommended for new designs. PIN DESCRIPTION Pin Number Pin Name Pin Function 12, 9 IN, /IN Differential Input: Internal 50 termination resistors to V input. Flexible input accepts any T differential input. See Input Interface Applications section. 1, 2, 3, 4 Q0, /Q0 Differential Buffered LVDS Outputs: Divided by 1, 2, 4, 8 or 16. See Truth Table. Q1, /Q1 Unused output pairs must be terminated with 100 across the different pair. 16, 15, 5 S0, S1, S2 Select Pins: See Truth Table. LVTTL/CMOS logic levels. Internal 25k pull-up resistor. Logic HIGH if left unconnected (divided by 16 mode.) Input threshold is V /2. CC 6 NC No Connect. 8 /RESET, LVTTL/CMOS Logic Levels: Internal 25k pull-up resistor. Logic HIGH if left unconnected. /DISABLE Apply LOW to reset the divider (divided by 2, 4, 8 or 16 mode). Also acts as a disable/enable function. The reset and disable function occurs on the next high-to-low clock input transition. Input threshold is V /2. CC 10 VREF-AC Reference Voltage: Equal to V 1.4V (approx.). Used for AC-coupled applications only. CC Decouple the VREFAC pin with a 0.01F capacitor. See Input Interface Applications section. 11 VT Termination Center-Tap: For CML or LVDS inputs, leave this pin floating. Otherwise, See Figures 4a to 4f Input Interface Applications section. 7, 14 VCC Positive Power Supply: Bypass with 0.1F//0.01F low ESR capacitor. 13 GND, Exposed Ground. Exposed pad must be connected to the same potential as the GND pin. pad TRUTH TABLE (1) /RESET S2 S1 S0 Outputs 1 0 X X Reference Clock (pass through) 1 1 0 0 Reference Clock 2 1 1 0 1 Reference Clock 4 1 1 1 0 Reference Clock 8 1 1 1 1 Reference Clock 16 (1) 0 X X X Q = LOW, /Q = HIGH Clock Disable Note: 1. Reset/Disable function is asserted on the next clock input (IN, /IN) high-to-low transition. M9999-082407 2 hbwhelp micrel.com or (408) 955-1690 S2 S0 NC S1 VCC VCC /RESET GND