TD9944 Dual N-Channel Enhancement-Mode Vertical DMOS FET Features General Description Dual N-channel devices This low threshold, enhancement-mode (normally-off) Low threshold 2.0V max. transistor utilizes a vertical DMOS structure and Supertexs High input impedance well-proven, silicon-gate manufacturing process. This combination produces a device with the power handling Low input capacitance 125pF max. capabilities of bipolar transistors and the high input Fast switching speeds impedance and positive temperature coefcient inherent Low on-resistance in MOS devices. Characteristic of all MOS structures, this Free from secondary breakdown device is free from thermal runaway and thermally-induced Low input and output leakage secondary breakdown. Applications Supertexs vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where Logic level interfaces ideal for TTL and CMOS very low threshold voltage, high breakdown voltage, high Solid state relays input impedance, low input capacitance, and fast switching Battery operated systems speeds are desired. Photo voltaic drives Analog switches General purpose line drivers Telecom switches Ordering Information Package Option R I V DS(ON) D(ON) GS(th) BV /BV 8-Lead SOIC DSS DGS Device (max) (min) (max) 4.90x3.90mm body (V) () (A) (V) 1.75mm height (max) 1.27mm pitch TD9944 TD9944TG-G 240 6.0 1.0 2.0 -G indicates package is RoHS compliant (Green) Pin Conguration D2 D2 D1 D1 G2 S2 Absolute Maximum Ratings G1 S1 Parameter Value 8-Lead SOIC (TG) Drain-to-source voltage BV DSS Product Marking Drain-to-gate voltage BV DGS Gate-to-source voltage 20V T D 9 9 YY = Year Sealed O O Operating and storage temperature -55 C to +150 C WW = Week Sealed 4 4 T G O Soldering temperature* 300 C Y Y W W = Green Packaging Absolute Maximum Ratings are those values beyond which damage to the device Package may or may not include the following marks: Si or may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All 8-Lead SOIC (TG) voltages are referenced to device ground. * Distance of 1.6mm from case for 10 seconds. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.comTD9944 O Electrical Characteristics (T = 25 C unless otherwise specied) A Sym Parameter Min Typ Max Units Conditions BV Drain-to-source breakdown voltage 240 - - V V = 0V, I = 2.0mA DSS GS D V Gate threshold voltage 0.6 - 2.0 V V = V , I = 1.0mA GS(th) GS DS D O V Change in V with temperature - - -5.0 mV/ C V = V , I = 1.0mA GS(th) GS(th) GS DS D I Gate body leakage - - 100 nA V = 20V, V = 0V GSS GS DS - - 10 A V = 0V, V = Max Rating GS DS I Zero gate voltage drain current DSS V = 0.8Max Rating, DS - - 1.0 mA V = 0V, T = 125C GS A 0.5 1.9 - V = 4.5V, V = 25V GS DS I ON-state drain current A D(ON) 1.0 2.8 - V = 10V, V = 25V GS DS - 4.0 6.0 V = 4.5V, I = 250mA GS D R Static drain-to-source on-state resistance DS(ON) - 4.0 6.0 V = 10V, I = 0.5A GS D O R Change in R with temperature - - 1.4 %/ C V = 10V, I = 0.5A DS(ON) DS(ON) GS D G Forward transductance 300 600 - mmho V = 20V, I = 0.5A FS DS D C Input capacitance - 65 125 ISS V = 0V, GS C Common source output capacitance - 35 70 pF V = 25V, OSS DS f = 1.0MHz C Reverse transfer capacitance - 10 25 RSS t Turn-on delay time - - 10 d(ON) V = 25V, DD t Rise time - - 10 r I = 1.0A, ns D t Turn-off delay time - - 20 d(OFF) R = 25 GEN t Fall time - - 20 f V Diode forward voltage drop - - 1.8 V V = 0V, I = 1.0A SD GS SD t Reverse recovery time - 300 - ns V = 0V, I = 1.0A rr GS SD Notes: O 1. All D.C. parameters 100% tested at 25 C unless otherwise stated. (Pulse test: 300s pulse, 2% duty cycle.) 2. All A.C. parameters sample tested. Switching Waveforms and Test Circuit V DD 10V 90% R L INPUT PULSE GENERATOR 10% 0V OUTPUT t t (ON) (OFF) R GEN t t t t d(ON) r d(OFF) F V DD D.U.T. 10% 10% INPUT OUTPUT 0V 90% 90% 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 2