ZL30105QDG1 Microchip

ZL30105 T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTCA and H.110 Data Sheet April 2010 Features Synchronizes to clock-and-sync-pair to maintain Ordering Information minimal phase skew between the master-clock and the redundant slave-clock ZL30105QDG1 64 pin TQFP* Trays Bake & Drypack Supports ITU-T G.813 option 1, G.823 for * Pb Free Matte Tin 2048 kbit/s and G.824 for 1544 kbit/s interfaces -40C to +85C Supports Telcordia GR-1244-CORE Stratum 3/4/4E Supports ANSI T1.403 and ETSI ETS 300 011 for Less than 0.6 ns intrinsic jitter on all output pp ISDN primary rate interfaces clocks and frame pulses Accepts three input references and synchronizes Manual or Automatic hitless reference switching to any combination of 2 kHz, 8 kHz, 1.544 MHz, between any combination of valid input reference 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz frequencies inputs Provides Lock, Holdover and selectable Out of Provides a range of clock outputs: 1.544 MHz Range indication (DS1), 2.048 MHz (E1), 3.088 MHz, 16.384 MHz, Simple hardware control interface and 19.44 MHz (SDH), and either 4.096 MHz and Selectable external master clock source: Clock 8.192 MHz or 32.768 MHz and 65.536 MHz, and a Oscillator or Crystal choice of 6.312 MHz (DS2), 8.448 MHz (E2), 44.736 MHz (DS3) or 34.368 MHz (E3) Provides 5 styles of 8 kHz framing pulses and a Applications 2 kHz multi-frame pulse Synchronization and timing control for multi-trunk -8 Holdover frequency accuracy of 1x10 SDH and T1/E1 systems such as DSLAMs, Selectable loop filter 1.8 Hz, 3.6 Hz or 922 Hz Gateways and PBXs Less than 24 ps intrinsic jitter on the 19.44 MHz rms Clock and frame pulse source for output clock, compliant with GR-253-CORE OC-3 AdvancedTCA- and other time division and G.813 STM-1 specifications multiplex (TDM) buses FASTLOCK LOCK OSCi OSCo TIE CLR OUT SEL2 Master Clock C2o C4/C65o Virtual REF0 TIE Reference C8/C32o REF1 MUX Corrector C16o Circuit E1 REF2 DPLL Synthesizer F4/F65o REF2 SYNC F8/F32o F16o REF FAIL0 TIE C1.5o Reference DS1 Corrector REF FAIL1 Monitor Synthesizer Enable C3o REF FAIL2 C19o SDH Synthesizer F2ko Mode Control C6/8.4/34/44o Programmable REF SEL1:0 Synthesizer OUT SEL1:0 State Machine Frequency RST Select MUX IEEE TRST 1149.1a MODE SEL1:0 HMS HOLDOVER SEC MSTR APP SEL1:0 TCK TDI TMS TDO Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004-2010, Zarlink Semiconductor Inc. All Rights Reserved.ZL30105 Data Sheet Description The ZL30105 SDH/PDH System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for SDH and T1/E1 transmission equipment. It provides advanced support for systems deploying redundant clocks. The ZL30105 generates SBI, ST-BUS and other TDM clock and framing signals that are phase locked to one of three network references or to a system master-clock reference. It helps ensure system reliability by monitoring its references for frequency accuracy and stability and by maintaining tight phase alignment between the master-clock and slave-clock outputs even in the presence of high network jitter. The ZL30105 is intended to be the central timing and synchronization resource for network equipment that complies with ITU-T, Telcordia, ETSI and ANSI network specifications. 2 Zarlink Semiconductor Inc.