ZL30142 SyncE SONET/SDH G.8262/Stratum 3 System Synchronizer Short Form Data Sheet July 2009 Features Ordering Information Supports the requirements of ITU-T G.8262 for ZL30142GGG 64 Pin CABGA Trays synchronous Ethernet Equipment slave Clocks ZL30142GGG2 64 Pin CABGA* Trays (EEC option 1 and 2) *Pb Free Tin/Silver/Copper Supports the requirements of Telcordia GR-1244 o o -40 C to +85 C Stratum 3 and GR-253, ITU-T G.812, G.813 Supports ITU-T G.823, G.824 and G.8261 for 2048 Flexible input reference monitoring automatically kbit/s and 1544 kbit/s interfaces disqualifies references based on frequency and Meets the SONET/SDH jitter generation phase irregularities requirements up to OC-48/STM-16 Provides automatic reference switching and Synchronizes to telecom reference clocks (2 kHz, holdover during loss of reference input N*8 kHz up to 77.76 MHz, 155.52 MHz) or to Supports master/slave configuration and dynamic Ethernet reference clocks (25 MHz, 50 MHz, input to output delay compensation for 62.5 MHz, 125 MHz) TM AdvancedTCA Generates standard SONET/SDH clock rates (e.g., Configurable input to output delay and output to 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz, output phase alignment 622.08 MHz) or Ethernet clock rates (e.g., 25 MHz, 50 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for Applications synchronizing Gigabit Ethernet PHYs Programmable output synthesizer generates ITU-T G.8262 System Timing Cards which support telecom clock frequencies from any multiple of 1 GbE interfaces 8 kHz up to 100 MHz Telcordia GR-253 Carrier Grade SONET/SDH Generates several styles of telecom frame pulses Stratum 3 System Timing Cards with selectable pulse width, polarity and frequency Internal state machine automatically controls mode of operation (free-run, locked, holdover) osci osco /N1 SONET/ ref0 diff ref1 /N2 Ethernet ref ref2 apll clk APLL DPLL Programmable sync0 p clk Synthesizer sync1 sync p fp N*8kHz sync2 2 mode lock hold I C/SPI JTAG Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2009, Zarlink Semiconductor Inc. All Rights Reserved.ZL30142 Short Form Data Sheet 1.0 High Level Overview The ZL30142 SONET/SDH/GbE Stratum 3 System Synchronizer and SETS device is a highly integrated device that provides all of the functionality that is required for a central timing card in carrier grade network equipment. The basic functions of a central timing card include: Input reference monitoring for both frequency accuracy and phase irregularities Automatic input reference selection Support of both external timing and line timing modes Hitless reference switching Wander and jitter filtering Master/slave crossover for minimizing phase alignment between redundant timing cards Independent derived output timing path for support of the SETS functionality In a typical application, the main timing path uses the DPLL to synchronize to either an external BITS source or to a recovered line timed source. The DPLL monitors the references and automatically selects the best available reference based on configurable priority and revertive properties. the DPLL provides the wander filtering function and the P0 synthesizer generates a jitter filtered clock and frame pulse for the system timing bus which supplies all line cards with a common timing reference. BIT S A BIT S B Central Central Tim ing Tim ing S P PS Card Card ZL30142 ZL30142 XO VER DPLL DPLL PS 19.44 M H z 19.44 M H z S P Lin e R e c o v e re d T im ing Telecom S A B B ackplane P S y stem T im in g B u s A A B B 19.4 4 M H z 19.44 M H z Prog ZL30146 ZL30146 Synth Prog Synth Tx Tx DPLL DPLL Rx Rx DPLL DPLL AP LL APLL 8 kH z 622 .0 8 M H z 15 6.25 M H z 25 M H z PH Y PH Y OC -192 10G bE Lin e C a rd Line C a rd Figure 2 - Typical Application of the ZL30142 2 Zarlink Semiconductor Inc.