ZL30145 SyncE (10 GbE) SONET/SDH Rate Conversion and Jitter Attenuator PLL Data Sheet March 2013 Features Ordering Information Can be used in systems to support the ZL30145GGG 64 Pin CABGA Trays requirements of ITU-T G.8262 for synchronous ZL30145GGG2 64 Pin CABGA* Trays Ethernet Equipment slave Clocks (EEC option 1 *Pb Free Tin/Silver/Copper and 2) o o -40 C to +85 C Meets jitter generation requirements of Telcordia GR-253-CORE for OC-192, OC-48, OC-12 and 2 Configurable through a serial interface (SPI or I C) OC-3 rates DPLL can be configured to provide synchronous or Meets jitter generation requirements of ITU-T G.813 asynchronous clock outputs for STM-64, STM-16, STM-4 and STM-1 rates Supports IEEE 1149.1 JTAG Boundary Scan Synchronizes to standard telecom or Ethernet clock and provides jitter filtered output clock for SONET/SDH and Synchronous Ethernet line cards Applications Synchronizes to telecom reference clocks (2 kHz, ITU-T G.8262 Line Cards which support 1 GbE N*8 kHz up to 77.76 MHz, 155.52 MHz) or to and 10 GbE interfaces Ethernet reference clocks (25 MHz, 50 MHz, 62.5 MHz, 125 MHz) SONET line cards up to OC-192 Generates standard SONET/SDH clock rates (e.g., SDH line cards up to STM-64 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz, 622.08 MHz) or Ethernet clock rates (e.g., 25 MHz, 50 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for synchronizing Ethernet PHYs Selectable loop bandwidth of 14 Hz, 28 Hz, or 890 Hz osci osco SONET/SDH/ diff Ethernet DPLL ref /N ref apll clk APLL 2 hold lock I C/SPI JTAG Figure 1 - Simplified Functional Block Diagram 1 Copyright 2013, Microsemi Corporation. All Rights Reserved.ZL30145 Data Sheet Table of Contents 1.0 Pin Diagram 14 2.0 High Level Overview . 15 2.1 DPLL Features . 15 2.2 DPLL Mode Control 16 2.3 Loop Bandwidth . 16 2.4 Reference Input . 17 2.5 Reference Monitoring 17 2.6 Reference Monitoring for Custom Configurations . 18 2.7 Output Clocks 21 2.7.1 Output Clock Squelching . 22 2.7.2 Disabling Output Clocks 22 2.8 Configurable Input-to-Output and Output-to-Output Delays . 22 2.9 Master Clock Interface 23 2.10 Clock Oscillator 23 2.11 Power Up/Down Sequence . 23 2.12 Power Supply Filtering . 24 2.13 Reset Circuit 24 2.14 APLL Filter Components and Recommended Layout . 24 2.15 Serial Interface 26 2.15.1 Serial Peripheral Interface . 26 2.15.2 SPI Functional Waveforms . 27 2.15.3 I2C Interface 28 3.0 Software Configuration . 30 3.0.1 Interrupts . 30 3.0.2 Multi-byte Register Values 30 4.0 Detailed Register Map 34 5.0 AC and DC Electrical Characteristics . 50 6.0 Thermal Characteristics 60 2 Microsemi Corporation