ZL30152 Universal Rate Adapting Synchronous Clock Generator Data Sheet March 2015 Features Ordering Information Programmable synthesizers generate any clock- ZL30152GGG2 64 Pin LBGA* Trays rate from 1 kHz to 750 MHz *Pb Free Tin/Silver/Copper o o Precision synthesizers generate clocks with jitter -40 C to +85 C below 0.7 ps RMS for 10 G PHYs Programmable digital PLL synchronize to any clock including input/output frequencies, is available via rate from 1 kHz to 750 MHz OTP(One Time Programmable) memory Flexible two-stage architecture translates between Dynamically configurable via SPI/I2C interface arbitrary data rates, line coding rates and FEC and volatile configuration registers rates Digital PLL filter jitter from 14 Hz, 28 Hz, 56 Hz, 112 Hz, 224 Hz, 448 Hz or 896 Hz Automatic hitless reference switching and digital holdover on reference fail Two reference inputs configurable as single ended or differential Four LVPECL outputs and two LVCMOS outputs Operates from a single crystal resonator or clock oscillator Customer defined default device configuration, Figure 1 - Functional Block Diagram 1 Copyright 2015, Microsemi Corporation. All Rights Reserved.ZL30152 Data Sheet Applications Clock Generation for Physical Line Interface: SONET/SDH, OC-192/OC-48 SONET/SDH with FEC 10G Base X, R and W 100 BaseX, GE, Fibre channel Clock Generation and Distribution for back plane Interface: TDM, Telecom Bus, Utopia, SBI Rapid-IO, PCI-Express, serial MII, Star Fabric, XAUI 2 Microsemi Corporation