ZL30159 General Purpose Clock Rate Converter Data Sheet March 2015 Features Ordering Information Precision synthesizer generates any clock-rate ZL30159GGG2 64 Pin LBGA* Trays from 1 Hz to 177.5 MHz with jitter below 1ps *Pb Free Tin/Silver/Copper Programmable digital PLL synchronize to any clock o o -40 C to +85 C rate from 1 Hz (1 pps) to 750 MHz Input reference configurable as single ended LVCMOS (up to 177.5 MHz) or differential LVPECL Customer defined default device configuration, (up to 750 MHz) including input/output frequencies, is available via OTP(One Time Programmable) memory Flexible two-stage architecture translates between arbitrary data rates, line coding rates and FEC Dynamically configurable via SPI/I2C interface rates and volatile configuration registers Programmable Digital PLL loop filter: 30 mHz, 14 Hz, 28 Hz, 56 Hz, 112 Hz, 224 Hz, 448 Hz or Applications 896 Hz General purpose clock rate translator Two LVCMOS outputs from 1 Hz (1 pps) to GPS receiver clock synthesizer 177.5 MHz Operates from a single crystal resonator or clock oscillator Figure 1 - Functional Block Diagram 1 Copyright 2015, Microsemi Corporation. All Rights Reserved.ZL30159 Data Sheet Table of Contents 1.0 Pin Diagram . 6 2.0 Pin Description . 7 3.0 Application Example . 11 4.0 Functional Description . 12 4.1 Input Sources 12 4.2 Input Reference Monitoring 12 4.2.1 DPLL General Characteristics . 14 4.2.2 DPLL States . 15 4.2.3 DPLL Rate Conversion Function and FEC Support . 16 4.2.4 DPLL Input to Output And Output to Output Phase Alignment 16 4.3 Frequency Synthesis Engine . 17 4.4 Dividers and Skew Management 17 4.5 Output Multiplexer . 18 4.6 Output Drivers 18 4.7 Input Buffers . 18 4.8 Master Clock Interface 21 4.9 Clock Oscillator . 21 4.10 Power Up/Down Sequence . 22 4.11 Power Supply Filtering . 22 4.12 Reset and Configuration Circuit 22 4.13 Ultra Low Jitter Synthesizer Filter Components and Recommended Layout . 23 5.0 Configuration and Control 24 5.1 Custom OTP Configuration 24 5.2 GPIO Configuration and Programmability . 24 5.3 Configuration Registers . 26 5.3.1 Input Reference Configuration and Programmability 27 5.3.2 DPLL Configuration and Programmability 27 5.3.3 Synthesis Macro Configuration and Programmability . 27 5.3.4 Output Dividers and Skew Management Configuration and Programmability . 27 5.3.5 Output Drivers configuration and Programmability .27 5.4 State Control . 27 5.4.1 Un-managed Mode . 28 5.4.2 Managed Mode 28 6.0 Host Interface . 29 6.1 Serial Peripheral Interface . 29 6.1.1 Least Significant Bit (LSB) First Transmission Mode 30 6.1.2 Most Significant Bit (MSB) First Transmission Mode 30 6.1.3 SPI Burst Mode Operation 31 6.1.4 I2C Interface . 31 7.0 Register Map . 33 8.0 Detailed Register Map 38 9.0 AC and DC Electrical Characteristics . 73 10.0 Performance Characterization 80 10.1 Output Clocks Jitter Generation . 80 10.2 DPLL Performance Characteristics . 81 11.0 Thermal Characteristics . 81 12.0 Package Markings 83 12.1 64-pin BGA. Package Top Mark Format . 83 2 Microsemi Corporation