Register Map: Section 6.2 ZL30264-ZL30267 2-APLL, 6- or 10-Output Any-to-Any Clock Multiplier and Frequency Synthesizer Data Sheet September 2020 Features Ordering Information Four Flexible Input Clocks ZL30264LDG1 ext. EEPROM 6 Outputs Trays ZL30264LDF1 ext. EEPROM 6 Outputs Tape and Reel One crystal/CMOS input ZL30265LDG1 int. EEPROM 6 Outputs Trays ZL30265LDF1 int. EEPROM 6 Outputs Tape and Reel Two differential/CMOS inputs ZL30266LDG1 ext. EEPROM 10 Outputs Trays ZL30266LDF1 ext. EEPROM 10 Outputs Tape and Reel One single-ended/CMOS input ZL30267LDG1 int. EEPROM 10 Outputs Trays ZL30267LDF1 int. EEPROM 10 Outputs Tape and Reel Any input frequency from 9.72MHz to 1.25GHz Matte Tin (300MHz max for CMOS) Package size: 8 x 8 mm, 56 Pin QFN -40 C to +85 C Activity monitors, automatic or manual switching Glitchless clock switching by pin or register Per-output enable/disable and glitchless 6 or 10 Any-Frequency, Any-Format Outputs start/stop (stop high or low) Any output frequency from 1Hz to 1045MHz General Features 2 fractional-N APLLs with 0ppm error Automatic self-configuration at power-up from external (ZL30264 or 6) or internal (ZL30265 or 7) Each APLL has a fractional divider and an EEPROM up to 8 configurations pin-selectable integer divider to make a total of four independent frequency families External feedback for zero-delay applications Output jitter from integer multiply and dividers Numerically controlled oscillator mode as low as 0.17ps RMS (12kHz-20MHz) Spread-spectrum modulation mode Output jitter from fractional dividers is typically Generates PCIe 1, 2, 3, 4 compliant clocks < 1ps RMS, many frequencies <0.5ps RMS Easy-to-configure design requires no external Each output has an independent divider VCXO or loop filter components Each output configurable as LVDS, LVPECL, 2 SPI or I C processor Interface HCSL, 2xCMOS or HSTL Core supply voltage options: 2.5V only, 3.3V In 2xCMOS mode, the P and N pins can be only, 1.8V+2.5V or 1.8V+3.3V different frequencies (e.g. 125MHz and 25MHz) Space-saving 8x8mm QFN56 (0.5mm pitch) Multiple output supply voltage banks with Applications CMOS output voltages from 1.5V to 3.3V Frequency conversion and frequency synthesis in Precise output alignment circuitry and per- a wide variety of equipment types output phase adjustment VDDOA IC1P, IC1N DIV OC1P, OC1N Int DIV DIV1 IC2P, IC2N DIV APLL1 IC3P DIV OC2P, OC2N DIV2 Fractional-N XA xtal DIV VDDOB Frac DIV driver XB x2 Figure 5 OC3P, OC3N DIV3 VDDOC bypass OC4P, OC4N DIV4 Int DIV APLL2 OC5P, OC5N DIV5 VDDOD 10-output Fractional-N OC6P, OC6N devices only Frac DIV DIV6 RSTN AC0/GPIO0 OC7P, OC7N bypass DIV7 AC1/GPIO1 Microprocessor VDDOE AC2/GPIO2 Port OC8P, OC8N DIV8 TEST/GPIO3 (SPI or I2C Serial) VDDOF IF0/CSN OC9P, OC9N and GPIO Pins DIV9 IF1/MISO SCL/SCLK OC10P, OC10N DIV10 SDA/MOSI Figure 1 - Functional Block Diagram 1 Microsemi Confidential Copyright 2018. Microsemi Corporation. All Rights Reserved. ZL30264-ZL30267 Data Sheet Table of Contents 1. APPLICATION EXAMPLE ............................................................................................................ 5 2. DETAILED FEATURES ................................................................................................................. 5 2.1 INPUT CLOCK FEATURES .............................................................................................................. 5 2.2 APLL FEATURES .......................................................................................................................... 5 2.3 OUTPUT CLOCK FEATURES ........................................................................................................... 5 2.4 GENERAL FEATURES .................................................................................................................... 5 2.5 EVALUATION SOFTWARE ............................................................................................................... 6 3. PIN DIAGRAM ............................................................................................................................... 7 4. PIN DESCRIPTIONS ..................................................................................................................... 8 5. FUNCTIONAL DESCRIPTION .................................................................................................... 10 5.1 DEVICE IDENTIFICATION .............................................................................................................. 10 5.2 PIN-CONTROLLED AUTOMATIC CONFIGURATION AT RESET ........................................................... 10 5.2.1 ZL30264 and ZL30266 Internal ROM, External or No EEPROM ...................................................... 11 5.2.2 ZL30265 and ZL30267 Internal EEPROM ........................................................................................ 11 5.3 LOCAL OSCILLATOR OR CRYSTAL ................................................................................................ 12 5.3.1 External Oscillator ................................................................................................................................ 12 5.3.2 External Crystal and On-Chip Driver Circuit ........................................................................................ 12 5.3.3 Clock Doublers ..................................................................................................................................... 13 5.3.4 Ring Oscillator (for Auto-Configuration) ............................................................................................... 14 5.4 INPUT SIGNAL FORMAT CONFIGURATION ...................................................................................... 14 5.5 APLL CONFIGURATION ............................................................................................................... 14 5.5.1 APLL Input Frequency ......................................................................................................................... 14 5.5.2 APLL Input Monitors ............................................................................................................................. 14 5.5.3 APLL Input Selection ............................................................................................................................ 14 5.5.4 APLL Output Frequency....................................................................................................................... 16 5.5.5 Fractional Output Divider ..................................................................................................................... 17 5.5.6 Numerically Controlled Oscillator (NCO) Mode ................................................................................... 18 5.5.6.1 Using the APLLs Feedback Divider ................................................................................................ 18 5.5.6.2 Using the Fractional Output Divider ................................................................................................. 18 5.5.7 Frequency Increment and Decrement ................................................................................................. 19 5.5.8 Spread-Spectrum Modulation Mode .................................................................................................... 19 5.5.8.1 Using the APLLs Feedback Divider ................................................................................................ 19 5.5.8.2 Using the Fractional Output Divider ................................................................................................. 20 5.5.9 APLL Phase Adjustment ...................................................................................................................... 21 5.6 OUTPUT CLOCK CONFIGURATION ................................................................................................ 21 5.6.1 Output Enable, Signal Format, Voltage and Interfacing ...................................................................... 21 5.6.2 Output Frequency Configuration .......................................................................................................... 22 5.6.3 Output Duty Cycle Adjustment ............................................................................................................. 23 5.6.4 Output Phase Adjustment .................................................................................................................... 23 5.6.5 Output-to-Output Phase Alignment ...................................................................................................... 23 5.6.6 Output-to-Input Phase Alignment ......................................................................................................... 23 5.6.7 Output Clock Start and Stop ................................................................................................................ 23 5.7 MICROPROCESSOR INTERFACE ................................................................................................... 24 5.7.1 SPI Slave ............................................................................................................................................. 24 5.7.2 SPI Master (ZL30264 and ZL30266 Only) ........................................................................................... 26 2 5.7.3 I C Slave .............................................................................................................................................. 27 5.8 INTERRUPT LOGIC ...................................................................................................................... 29 5.9 RESET LOGIC ............................................................................................................................. 30 5.9.1 Design Considerations for Using an External RC Reset Circuit .......................................................... 30 2 Microsemi Confidential