ZL30312 Combined Synchronous Ethernet and IEEE1588 Network Synchronization Data Sheet October 2012 Features Supports the combination of SyncE for frequency Ordering Information synchronization and IEEE 1588 for phase alignment ZL30312GKG 256 TEPBGA, 17 x 17 mm (referred to as Hybrid Mode) ZL30312GKG2* 256 TEPBGA, 17 x 17 mm * PB Free Tin/Silver/Copper Recovers and transmits network synchronization over Ethernet, IP and MPLS Networks -40C to +85C Simultaneously supports both the Synchronous Accepts eight input references, and up to three Ethernet (Option 1 and Option 2 and the IEEE 1588 associated low frequency alignment or framing industry standard timing protocols pulses Capable of server, client repeater, and boundary Generates up to four separate output clocks at clock operation frequencies between 8 kHz and 100 MHz Integrates two separate digital phase locked loops, Generates two separate Synchronous Ethernet with hitless switching between packet and electrical clocks to drive industry standard Ethernet PHY clock references devices at either 25 MHz or 125 MHz Primary DPLL meets Stratum 2 and 3/SONET Fully configurable solution, enabling performance quality to be tailored to application/network requirements Targeted for synchronization distribution to better Two independently configurable MAC interfaces, than ITU-T G.8261, G.823, G.824 and ANSI T1.101 supporting MII, RMII, GMII and TBI standards synchronization interface standards Wire-speed Ethernet Bridge pass through function Average frequency accuracy better than 10 ppb between the MAC interfaces Aligns to a low frequency input signal at server Synchronous serial control interface (e.g., 1 Hz) with targeted accuracy better than 1 s Full demonstration & evaluation platform available Recovers clocks from two independent servers, with hitless switching between packet streams for redundancy Supports holdover if the server stream is lost ToP Port M2 Port M1 Network I/F MAC Ethernet Bridge MAC Processor I/F (GMII/TBI/MII/RMII) (GMII/TBI/MII/RMII) osci Master Register SSI Timestamp Engine Osc Access I/F osco PLL ref0 ETH CLK0 ref1 APLL ETH CLK1 ref n ref2 DPLL 1 ref3 Stratum 3E sync n p0 clk0 Input Ports ref4 P0 p0 clk1 ref5 & Synthesizer p0 fp0 ref6 Ref p0 fp1 ref7 Monitors refm P1 p1 clk0 DPLL2 sync0 p1 clk1 Synthesizer sync1 sync2 Figure 1 - ZL30312 Functional Block Diagram 1 Copyright 2012, Microsemi Corporation. All Rights Reserved.ZL30312 Data Sheet Applications IEEE 1588 and Synchronous Ethernet timing GSM and UMTS air interface synchronization over a packet network Circuit Emulation Services over Packets IP-PBX and VoIP Gateways Video Conferencing Broadband Video Distribution 2 Microsemi Corporation