ZL30363 IEEE 1588 and Synchronous Ethernet Packet Clock Network Synchronizer Short Form Data Sheet May 2013 Features Ordering Information: Two independent clock channels ZL30363GDG2 144 Pin LBGA Trays Frequency and Phase Sync over Packet Networks Frequency accuracy performance for WCDMA- Pb Free Tin/Silver/Copper o o FDD, GSM, LTE-FDD and femtocell applications -40 C to +85 C Package size: 13 x 13 mm Frequency performance for ITU-T G.823 and G.824 synchronization interface, as well as Any input clock rate from 1 Hz to 750 MHz G.8261 PNT PEC and CES interfaces Automatic hitless reference switching and digital Phase Synchronization performance for holdover on reference fail WCDMA-TDD, Mobile WiMAX, TD-SCDMA and Flexible two-stage architecture to support CDMA2000 applications conversion between SONET/SDH and OTN rates Client holdover and reference switching Digital PLLs with programmable bandwidth from between multiple Servers 0.1 mHz up to 1 kHz Physical Layer Equipment Clocks Synchronization Programmable synthesizers ITU-T G.8262 for SyncE EEC option 1 and 2 Any output clock rate from 1 Hz to 750 MHz with maximum jitter below 0.63 ps RMS ITU-T G.813 for SONET/SDH SEC option 1 and 2 Operates from a single crystal resonator or clock oscillator Telcordia GR-1244 and GR-253 Stratum 3 and 2 Configurable via SPI/I C interface SMC Support for G.781 SETS Osci Master Clock Clock Generator 0 Div A Osco LVPECL hpdiff0 p/n ZL30363 Div B LVPECL hpdiff1 p/n Diff / Single Ended Synthesizer 0 Ref0 Fr = Br *Kr *Mr /Nr hpoutclk0 0 0 0 0 0 Fs= Bs *Ks *16*Ms /Ns Div C LVCMOS 0 0 0 0 Diff / Single Ended Div D LVCMOS hpoutclk1 Ref1 Fr1= Br1*Kr1*Mr1/Nr1 Diff / Single Ended Ref2 Fr2= Br2*Kr2*Mr2/Nr2 Clock Generator 1 Div A LVPECL hpdiff2 p/n Diff / Single Ended Ref3 Div B LVPECL hpdiff3 p/n Fr3= Br3*Kr3*Mr3/Nr3 Synthesizer 1 Fs= Bs *Ks *16*Ms /Ns hpoutclk2 1 1 1 1 Div C LVCMOS Diff / Single Ended Ref4 DPLL0/NCO0 Fr4= Br4*Kr4*Mr4/Nr4 Div D LVCMOS hpoutclk3 Select Loop band., Diff / Single Ended Phase slope limit Ref5 Fr5= Br5*Kr5*Mr5/Nr5 DPLL1/NCO1 Clock Generator 2 Diff / Single Ended Div A LVPECL hpdiff4 p/n Ref6 Select Loop band., Fr = Br *Kr *Mr /Nr 6 6 6 6 6 Phase slope limit Div B LVPECL hpdiff5 p/n Synthesizer 2 Diff / Single Ended Ref7 Fs= Bs *Ks *16*Ms /Ns Div C LVCMOS hpoutclk4 2 2 2 2 Fr = Br *Kr *Mr /Nr 7 7 7 7 7 Diff / Single Ended Div D LVCMOS hpoutclk5 Ref8 Fr = Br *Kr *Mr /Nr 8 8 8 8 8 Single Ended Ref9 Clock Generator 3 Fr = Br *Kr *Mr /Nr Div A LVPECL 9 9 9 9 9 hpdiff6 p/n Single Ended Div B LVPECL hpdiff7 p/n Ref10 Synthesizer 3 Fr = Br *Kr *Mr /Nr 10 10 10 10 10 State Configuration Fs= Bs *Ks *16*Ms /Ns hpoutclk6 3 3 3 3 Div C LVCMOS Machine and Status Div D LVCMOS hpoutclk7 JTAG Reference Monitors 2 JTAG pwr b GPIO SPI / I C Figure 1 - Functional Block Diagram 1 Copyright 2013, Microsemi Corporation. All Rights Reserved.ZL30363 Short Form Data Sheet Detailed Features General Two independent clock channels Operates from a single crystal resonator or clock oscillator 2 Configurable via its SPI/I C interface Time Synchronization Algorithm External algorithm controls software digital PLL to adjust frequency and phase alignment Frequency, Phase and Time Synchronization over IP, MPLS and Ethernet Packet Networks Frequency accuracy performance for WCDMA-FDD, GSM, LTE-FDD and femtocell applications, with target performance less than 15 ppb. Frequency performance for ITU-T G.823 and G.824 synchronization interface, as well as G.8261 PNT EEC, PNT PEC and CES interface specifications. Phase Synchronization performance for WCDMA-TDD, Mobile WiMAX, TD-SCDMA and CDMA2000 applications with target performance less than 1 s phase alignment. Time Synchronization for UTC-traceability and GPS replacement. Client reference switching between multiple Servers Client holdover when Server packet connectivity is lost Electrical Clock Inputs Nine input references configurable as single ended or differential and two single ended input references Synchronize to any clock rate from 1 Hz to 750 MHz on differential inputs Synchronize to any clock rate from 1 Hz to 177.75 MHz on singled-ended inputs Any input reference can be fed with sync (frame pulse) or clock. Synchronize to sync pulse and sync pulse/clock pair. Flexible input reference monitoring automatically disqualifies references based on frequency and phase irregularities LOS Single cycle monitor Precise frequency monitor Coarse frequency monitor Guard soak timer Per input clock delay compensation Electrical Clock Engine Digital PLLs filter jitter from 0.1 mHz up to 1 kHz Flexible two-stage architecture translates between arbitrary data rates, line coding rates and FEC rates Internal state machine automatically controls mode of operation (free-run, locked, holdover) Automatic hitless reference switching and digital holdover on reference fail Physical-to-physical reference switching 2 Microsemi Corporation