ZL30671, ZL30672, ZL30673 1-, 2-, 3-Channel, 10-Input, 18-Output System Synchronizers Product Brief November 2019 Features Ordering Information One, Two or Three DPLL Channels ZL30671LFG7 1-Channel 80-lead LGA Trays ZL30672LFG7 2-Channel 80-lead LGA Trays Timing compliance with ITU-T G.8262, G.813, ZL30673LFG7 3-Channel 80-lead LGA Trays G.812, G.8273.2 Telcordia GR-1244, GR-253 NiAu (Pb-free) Programmable bandwidth, 0.1mHz to 470Hz Package size: 11 x 11 mm Freerun or holdover on loss of all inputs -40 C to +85 C Hitless reference switching Per-output programmable duty cycle High-resolution holdover averaging Precise output alignment circuitry and per- Per-DPLL phase adjustment, 1ps resolution output phase adjustment Programmable tracking range, phase-slope limiting, frequency-change limiting and other Per-output enable/disable and glitchless advanced features start/stop (stop high or low) Local Oscillator Input Clocks Operates from a single TCXO or OCXO: 23.75- Accepts up to 10 differential or CMOS inputs 25MHz, 47.5-50MHz, 114.285-125MHz Any input frequency from 0.5Hz to 900MHz Very-low-jitter applications can connect a TCXO Per-input activity and frequency monitoring or OCXO as the stability reference and a low- Automatic or manual reference switching jitter XO as the jitter reference Revertive or nonrevertive switching General Features Any input can be a 1PPS SYNC input for Automatic self-configuration at power-up from REF+SYNC frequency/phase/time locking internal Flash memory Input-input phase measurement, 1ps resolution Input-to-output alignment <200ps (ext feedback) Input-DPLL phase measurement, 1ps resolution Fast REF+SYNC locking for frequency and Per-input phase adjustment, 1ps resolution 1PPS phase alignment with lower-cost oscillator Internal compensation (1ppt) for local oscillator Output Clock Frequency Generation frequency error in DPLLs and input monitors Any output frequency from <0.5Hz to 1045MHz Numerically controlled oscillator behavior in (180MHz max for Synth0) each DPLL and each fractional output divider High-resolution fractional frequency conversion Easy-to-configure design requires no external with 0ppm error VCXO or loop filter components Synthesizers 1 & 2 have integer and fractional 7 GPIO pins with many possible behaviors dividers to make a total of 5 frequency families 2 SPI or I C processor Interface Output jitter from Synth 1 & 2 is <0.3ps RMS 1.8V and 3.3V core VDD voltages Output jitter from fractional dividers is typically < 1ps RMS, many frequencies <0.5ps RMS Power: 1.3W for 2 inputs, 1 synth, 6 LVDS out Each HPOUTP/N pair can be LVDS, LVPECL, Easy-to-use evaluation/programming software HCSL, 2xCMOS, HSTL or programmable diff. In 2xCMOS mode, the P and N pins can be Applications different frequencies (e.g. 125MHz and 25MHz) Central system timing ICs for SyncE, SyncE+1588, SONET/SDH, OTN, wireless Four output banks each with VDDO pin CMOS base station and other carrier-grade systems output voltages from 1.5V to 3.3V G.8262/813 EEC/SEC, Telcordia Stratum 2-4 Per-synthesizer phase adjust, 1ps resolution 1 Microsemi Confidential Copyright 2019. Microsemi Corporation. All Rights Reserved. ZL30671, ZL30672, ZL30673 Data Sheet 1. Block Diagram DIV GPOUT0 GP Synthesizer 0 DPLL0 REF0P general purpose One Diff / Two DIV GPOUT1 REF0N Single-Ended REF1P HPOUT0P One Diff / Two IntDiv DIV REF1N Single-Ended HPOUT0N HP Synthesizer 1 DPLL1 low-jitte r HPOUT1P DIV REF2P One Diff / Two FracDiv HPOUT1N REF2N Single-Ended HPOUT2P DIV REF3P HPOUT2N One Diff / Two IntDiv REF3N Single-Ended HP Synthesizer 2 HPOUT3P DIV low-jitter HPOUT3N DPLL2 REF4P One Diff / Two FracDiv REF4N Single-Ended HPOUT4P DIV HPOUT4N HPOUT5P Reference Monitors DIV & State Machines HPOUT5N HPOUT6P DIV HPOUT6N Microprocessor Port Master XO HPOUT7P SPI or I2C I/F & GPIO Pins Clock Optional x2 DIV HPOUT7N DPLL1 only present on ZL30672 and ZL30673 DPLL2 only present on ZL30673 Figure 1 - Functional Block Diagram 2. Application Example TCXO 1.544 or 2.048MHz CMOS to BITS/SSU to BITS/SSU system DPLL0 Synth0 T4 path 1 PPS or clock w/ embedded PPS BITS/SSU 2x 156.25MHz GPS (1PPS) SyncE signals to DPLL1 2x 125MHz Synth1 system components SyncE Line 155.52MHz, 161.1328125MHz Extracted or other frequency Clocks 7:0 25MHz 1588 signals to DPLL2 Synth2 system components Control info from 1588 1 PPS IEEE 1588 algorithm Figure 2 - Synchronous Ethernet and IEEE 1588 Central Timing Application 2 Microsemi Confidential RST B SRST B GPIO 8:0 CS B ASEL0 SCK SCL SI SDA SO ASEL1 MCLKIN P MCLKIN N OSCI OSCO