Short Form Data Sheet ZL30701/ZL30702/ZL30703/ZL30704 IEEE 1588 & Synchronous Ethernet Packet Clock Network Synchronizer Ordering Information Features ZL30701LDG6* 100 Pin aQFN Trays Up to four independent clock channels ZL30702LDG6* 100 Pin aQFN Trays ZL30703LDG6* 100 Pin aQFN Trays Fully compliant to EEC (G.8262), SEC (G.813), GR-253 ZL30704LDG6* 100 Pin aQFN Trays *Pb Free Tin/Silver/Copper SMC and GR-1244 Stratum 3/3E Package size: 10 x 10 mm -40 C to +85 C Frequency accuracy performance for GSM, WCDMA- FDD, LTE-FDD basestations and small cell applications, Excellent jitter performance of 180 fs rms (12 kHz to 20 MHz) with target performance less than 15 ppb. meets 10G/40G and 100G PHY jitter requirements Frequency performance for ITU-T G.823 and G.824 Up to four programmable digital PLLs/NCOs with loop bandwidth synchronization interface, as well as G.8261 PNT EEC, from 0.1 mHz to 470 Hz synchronize to any clock rate from 0.5 Hz PNT PEC and CES interface specifications. to 900 MHz Phase Synchronization performance for WCDMA-TDD, Automatic hitless reference switching and digital holdover on TD-SCDMA, CDMA2000, LTE-TDD and LTE-A reference fail with initial holdover accuracy better than 0.1 ppb applications with target performance less than 1 s Any input reference can be fed with clock, sync (frame pulse), phase alignment. clock /sync pair or clock modulated with sync pulse (embedded Client holdover and reference switching between PPS ePPS and embedded PP2S ePP2S) multiple Servers Support for new ITU-T packet clock recommendations or drafts: G.8263 PEC-S, G.8273.2 T-BC, T-TSC, G.8273.4 T-BC-P, T-TSC-P & T-TSC-A ZL30701/ZL30702/ZL30703/ZL30704 OSCI Osc Master Clock OSC0 Clock Generator 0 Div A GPOUT0 LVCMOS PACKET REF 0:3 GP Synthesizer 0 DPLL0 Fs= Bs *Ks *Ms /Ns 0 0 0 0 REFIN0 0P GPOUT1 LVCMOS One Diff / Two Select Loop band., REFIN1 0N Div B Single Ended Phase slope limit One Diff / Two REFIN2 1P DPLL1 CML Clock Generator 1 Single Ended HPOUT0 0P REFIN3 1N Div A or Select Loop band., HPOUT1 0N Phase slope limit Div B 2 x LVCMOS HP Synthesizer 1 One Diff / Two REFIN4 2P CML Fs= Bs *Ks *Ms /Ns Div C 1 1 1 1 REFIN5 2N Single Ended HPOUT2 1P or HPOUT3 1N DPLL2 Div D 2 x LVCMOS Select Loop band., One Diff / Two REFIN6 3P Phase slope limit Single Ended REFIN7 3N CML Clock Generator 2 HPOUT4 2P Div A or HPOUT5 2N LVCMOS One Diff / Two REFIN8 4P HP Synthesizer 2 Single Ended DPLL3 REFIN9 4N Div B CML Fs= Bs *Ks *Ms /Ns 2 2 2 2 HPOUT6 3P Select Loop band., or Div C HPOUT7 3N Phase slope limit LVCMOS Div D Clock Generator 3 CML Osc HPOUT8 4P State Machine PartNumber AvailableDPLLs or HP Synthesizer 3 HPOUT9 4N Div A LVCMOS Fs= Bs *Ks *Ms /Ns 3 3 3 3 or CML ZL30701 DPLL 0 Reference Monitors SysClk HPOUT10 5P or Sys APLL Configuration HPOUT11 5N Div B ZL30702 DPLL 0,1 LVCMOS and Status JTAG Osc ZL30703 DPLL 0,1,2 ZL30704 DPLL 0,1,2,3 MCLKIN P 2 MCLKIN N SPI / I C JTAG PWR b GPIO Functional Block Diagram ZL30701/ZL30702/ZL30703/ZL30704 August 2016 1 Confidential 2016 Microsemi Corporation Short Form Data Sheet ZL30701/ZL30702/ZL30703/ZL30704 2 Feature List 2.1 General features Up to four independent clock channels Operates from a single crystal resonator or clock oscillator o Supports split XO mode for low-frequency stability TCXO/OCXO with ultra-low jitter clock outputs Configurable from SPI/I2C bus or from pre-configured flash memory 2.2 Electrical Clock Inputs Acceptsupto10LVCMOSor5LVDS/HCSL/LVPECL/CMLinputs Frequencies from 0.5 Hz to 180 MHz for LVCMOS Frequencies from 0.5 Hz to 900 MHz for LVDS/HCSL/LVPECL/CML Flexible input reference monitoring automatically disqualifies references based on frequency and phase irregularities. o Each input reference has its own set of monitors which can be independently programmed. o Loss of signal (LOS) o Single Cycle Monitor (Triggers on glitches or variation in duty-cycle) o Coarse Frequency Monitor o Precise Frequency Monitor Locks to gapped clocks 2.3 Electrical Clock Input-Output Special Formats Supports 64 kHz composite clocks with external glue logic Supports embedded pulse per second (ePPS) single wire for carrying high-speed clock & 1PPS Supports REF-SYNC pair, a combination of a high speed clock reference and a frame pulse sync pair Each output can generate clock, sync pulse, embedded pulse per second (ePPS) or embedded pulse per 2 seconds (ePP2S) o Clock modulated sync feature helps in reducing number of clock lines on backplane and in addition provides equal delay for both clock and sync signals. 2.4 Electrical Clock Engine Digital PLLs filter jitter from 0.1 mHz up to 470 Hz Multiple modes of operation o Freerun o Forced holdover o Forced reference o Automatic o NCO Internal state machine automatically controls state o Locked o Acquiring o Holdover Automatic hitless reference switching and digital holdover on reference fail o Physical-to-physical reference switching o Physical-to-packet reference switching o Packet-to-physical reference switching o Packet-to-packet reference switching Support for fast lock with lock times in seconds Support for hitless reference switching Internal, per DPLL, time of day counters maintaining full 48-bit seconds and 32-bit nanoseconds aligned to 1PPS rollover Holdover better than 0.01 ppb Full rate conversion between input and output clock frequencies Supports ITU-T G.823, G.824 and G.8261 for 2048 Kbit/s and 1544 Kbit/s interfaces Supports G.781 SETS August 2016 ZL30701/ZL30702/ZL30703/ZL30704 2 Confidential 2016 Microsemi Corporation