ZL30771, ZL30772, ZL30773 IEEE 1588 & Synchronous Ethernet Packet Clock Network Synchronizers Product Brief November 2019 Features Ordering Information One, Two or Three DPLL Channels ZL30771LFG7 1-Channel 80-lead LGA Trays Packet and/or physical-layer frequency, phase ZL30772LFG7 2-Channel 80-lead LGA Trays and time synchronization ZL30773LFG7 3-Channel 80-lead LGA Trays Physical-layer compliance with ITU-T G.8262, NiAu (Pb-free) G.8261.1, G.813, G.812, Telcordia GR-1244, Package size: 11 x 11 mm GR-253 -40 C to +85 C Packet-timing compliance with ITU-T G.8261, G.8263, G.8273.2 (class A, B, C, D), G.8273.4 Per-output programmable duty cycle Enables 5G wireless applications with sub- Precise output alignment circuitry and per- 100ns time/phase alignment requirements output phase adjustment Programmable bandwidth, 0.1mHz to 470Hz Per-output enable/disable and glitchless Hitless reference switching and mode switching start/stop (stop high or low) High-resolution holdover averaging Local Oscillator Programmable phase slope limit for transients, Operates from a single TCXO or OCXO: 23.75- downto 1 ns/s 25MHz, 47.5-50MHz, 114.285-125MHz Per-DPLL phase adjustment, 1ps resolution Very-low-jitter applications can connect a TCXO or OCXO as the stability reference and a low- Input Clocks jitter XO as the jitter reference Accepts up to 10 differential or CMOS inputs General Features Any input frequency from 0.5Hz to 900MHz Automatic self-configuration at power-up from Per-input activity and frequency monitoring internal Flash memory Automatic or manual reference switching Input-to-output alignment <2ns Fast lock to 1 PPS input, <30 seconds Internal compensation (1ppt) for local oscillator Any input can be a 1PPS SYNC input for frequency error in DPLLs and input monitors REF+SYNC frequency/phase/time locking Numerically controlled oscillator behavior in Per-input phase adjustment, 1ps resolution each DPLL and each fractional output divider Output Clock Frequency Generation Programmable Time of Day counters Any output frequency from <0.5Hz to 1045MHz Easy-to-configure design requires no external (180MHz max for Synth0) VCXO or loop filter components High-resolution fractional frequency conversion 7 GPIO pins with many possible behaviors with 0ppm error 2 SPI or I C processor Interface Synthesizers 1 & 2 have integer and fractional 1.8V and 3.3V core VDD voltages dividers to make a total of 5 frequency families Power: 1.3W for 2 inputs, 1 synth, 6 LVDS out Output jitter from Synths 1 & 2 is <0.3ps RMS Easy-to-use evaluation/programming software Output jitter from fractional dividers is typically < 1ps RMS, many frequencies <0.5ps RMS Factory programmable power-up configuration Each HPOUTP/N pair can be LVDS, LVPECL, Applications HCSL, 2xCMOS, HSTL or programable diff. Central system timing ICs for SyncE and/or Four output banks each with VDDO pin CMOS IEEE 1588, SONET/SDH, OTN, wireless base output voltages from 1.5V to 3.3V station and other carrier-grade systems Per-synthesizer phase adjust, 1ps resolution G.8262/813 EEC/SEC, Telcordia Stratum 2-4 1 Microsemi Confidential Copyright 2019. Microsemi Corporation. All Rights Reserved. ZL30771, ZL30772, ZL30773 Data Sheet 1. Block Diagram Register Access PACKET REF 2:0 DIV GPOUT0 GP Synthesizer 0 DPLL0 general purpose REF0P One Diff / Two DIV GPOUT1 REF0N Single-Ended REF1P HPOUT0P One Diff / Two IntDiv DIV REF1N Single-Ended HPOUT0N HP Synthesizer 1 DPLL1 low-jitte r HPOUT1P DIV REF2P One Diff / Two FracDiv HPOUT1N REF2N Single-Ended HPOUT2P DIV REF3P HPOUT2N One Diff / Two IntDiv REF3N Single-Ended HP Synthesizer 2 HPOUT3P DIV low-jitter HPOUT3N DPLL2 REF4P One Diff / Two FracDiv REF4N HPOUT4P Single-Ended DIV HPOUT4N HPOUT5P Reference Monitors DIV & State Machines HPOUT5N HPOUT6P DIV HPOUT6N Microprocessor Port Master XO HPOUT7P SPI or I2C I/F & GPIO Pins Clock Optional x2 DIV HPOUT7N DPLL1 only present on ZL30772 and ZL30773 DPLL2 only present on ZL30773 Figure 1 - Functional Block Diagram 2. Application Example 1.544 or 2.048MHz TCXO to BITS/SSU system CMOS to BITS/SSU DPLL0 Synth0 T4 path 1 PPS or clock w/ embedded PPS BITS/SSU 2x 156.25MHz GPS (1PPS) SyncE signals to DPLL1 2x 125MHz Synth1 system components SyncE Line 155.52MHz, 161.1328125MHz Extracted or other frequency Clocks 7:0 25MHz 1588 signals to DPLL2 Synth2 system components 1588 Control info from 1 PPS IEEE 1588 algorithm Figure 2 - Synchronous Ethernet and IEEE 1588 Central Timing Application 2 Microsemi Confidential RST B SRST B GPIO 8:0 CS B ASEL0 SCK SCL SI SDA SO ASEL1 MCLKIN P MCLKIN N OSCI OSCO