ZL40205LDG1 Microchip

ZL40205 Precision 1:6 LVPECL Fanout Buffer with On-Chip Input Termination Data Sheet April 2014 Features Ordering Information ZL40205LDG1 32 Pin QFN Trays ZL40205LDF1 32 Pin QFN Tape and Reel Inputs/Outputs Matte Tin Accepts differential or single-ended input Package Size: 5 x 5 mm o o LVPECL, LVDS, CML, HCSL, LVCMOS -40 C to +85 C On-chip input termination resistors and biasing for Applications AC coupled inputs General purpose clock distribution Six precision LVPECL outputs Low jitter clock trees Operating frequency up to 750 MHz Logic translation Power Clock and data signal restoration Options for 2.5 V or 3.3 V power supply Wired communications: OTN, SONET/SDH, GE, 10 GE, FC and 10G FC Core current consumption of 110 mA PCI Express generation 1/2/3 clock distribution On-chip Low Drop Out (LDO) Regulator for superior power supply rejection Wireless communications High performance microprocessor clock Performance distribution Ultra low additive jitter of 36 fs RMS out0 p out0 n out1 p out1 n ctrl Termination out2 p and Bias vt out2 n Buffer clk p out3 p out3 n clk n out4 p out4 n out5 p out5 n Figure 1 - Functional Block Diagram 1 Microsemi Corporation Copyright 2014, Microsemi Corporation. All Rights Reserved.ZL40205 Data Sheet Table of Contents Features . 1 Inputs/Outputs . 1 Power 1 Performance . 1 Applications . 1 Change Summary . 4 1.0 Package Description 5 2.0 Pin Description . 6 3.0 Functional Description 7 3.1 Clock Inputs . 7 3.2 Clock Outputs 12 3.3 Device Additive Jitter . 15 3.4 Power Supply 16 3.4.1 Sensitivity to power supply noise . 16 3.4.2 Power supply filtering 16 3.4.3 PCB layout considerations 16 4.0 AC and DC Electrical Characteristics . 17 5.0 Performance Characterization . 20 6.0 Typical Behavior 21 7.0 Package Characteristics . 23 8.0 Mechanical Drawing . 24 2 Microsemi Corporation