ZL40223LDG1 Microchip

ZL40223 Precision 2:8 LVDS Fanout Buffer with Glitch- free Input Reference Switching and On-Chip Input Termination Data Sheet November 2012 Features Ordering Information ZL40223LDG1 32 Pin QFN Trays Inputs/Outputs ZL40223LDF1 32 Pin QFN Tape and Reel Accepts two differential or single-ended inputs Matte Tin LVPECL, LVDS, CML, HCSL, LVCMOS Package size: 5 x 5 mm o o -40 C to +85 C Glitch-free switching of references On-chip input termination and biasing for AC Applications coupled inputs Eight precision LVDS outputs General purpose clock distribution Operating frequency up to 750 MHz Low jitter clock trees Logic translation Power Clock and data signal restoration Option for 2.5 V or 3.3 V power supply Redundant clock distribution Current consumption of 114 mA Wired communications: OTN, SONET/SDH, GE, On-chip Low Drop Out (LDO) Regulator for superior 10 GE, FC and 10G FC power supply rejection Wireless communications Performance High performance micro-processor clock Ultra low additive jitter of 165 fs RMS distribution out0 p out0 n out1 p ctrl0 out1 n Termination and Bias vt0 out2 p out2 n clk0 p clk0 n out3 p out3 n clk1 p Buffer clk1 n out4 p out4 n ctrl1 Termination and Bias vt1 out5 p out5 n out6 p sel out6 n out7 p out7 n Figure 1 - Functional Block Diagram 1 Microsemi Corporation Copyright 2012, Microsemi Corporation. All Rights Reserved. ControlZL40223 Data Sheet Table of Contents Features . 1 Applications . 1 1.0 Package Description 4 2.0 Pin Description . 5 3.0 Functional Description 6 3.1 Clock Inputs . 6 3.1.1 Clock Input Selection . 6 3.1.2 Clock Input Terminations 7 3.2 Clock Outputs 12 3.3 Device Additive Jitter . 15 3.4 Power Supply 16 3.4.1 Sensitivity to power supply noise . 16 3.4.2 Power supply filtering 16 3.4.3 PCB layout considerations 16 4.0 AC and DC Electrical Characteristics . 17 5.0 Performance Characterization . 19 6.0 Typical Behavior 20 7.0 Package Characteristics 21 8.0 Mechanical Drawing . 22 2 Microsemi Corporation