ZL40240LDG1 Microchip

Data Sheet ZL40240 Ten LVCMOS Output Low Additive Jitter Fanout Buffer Ordering Information Features ZL40240LDG1 32 Pin QFN Trays 3 to 1 input Multiplexer: Two inputs accept ZL40240LDF1 32 pin QFN Tape and Reel any differential (LVPECL, HCSL, LVDS, SSTL, CML, LVCMOS) or a single ended Package size: 5 x 5 mm signal and the third input accepts a crystal -40 C to +85 C or a single ended signal Ten 1.5V/1.8V/2.5V/3.3V LVCMOS outputs Applications General purpose clock distribution Supports frequencies from 0 to 250MHz Low jitter clock trees Ultra-low system level additive jitter: 17fs (12kHz to 20MHz) Logic translation Clock and data signal restoration Ultra-low noise floor of -170dBc/Hz Wired and Wireless communications Supports crystals from 8MHz to 160MHz High performance microprocessor clock distribution Supports 2.5V or 3.3V power supplies Medical Imaging Output to output skew of 30ps (typical) Test equipment Input to output delay of 2ns (typical) SPI or Hardware control SEL SPI Slave xtal buf gain 7:0 OE xtal drive level 7:0 OE/SPI CS b SPI CS b OUT0 xtal load cap 7:0 input select 1:0 output drive low output enable 4:0 IN SEL0 IN SEL0/ output enable 9:5 SPI CLK OUT1 driver strength 4:0 SPI CLK driver strength 9:5 IN SEL1 Device ID IN SEL1/ SPI SDIO SPI SDIO OUT2 IN0 p IN0 n OUT3 00 SYNC IN1 p 01 IN1 n OUT4 10 11 OUT5 XOUT OUT6 XIN OUT7 ZL40240 OUT8 OUT9 Figure 1. Functional Block Diagram February 2017 1 ZL40240 2017 Microsemi Corporation Data Sheet ZL40240 Table of Contents Features ..................................................................................................................................... 1 Table of Contents ...................................................................................................................... 2 Pin Diagram ............................................................................................................................... 5 Pin Descriptions ......................................................................................................................... 6 Functional Description ............................................................................................................... 9 Clock Inputs ............................................................................................................................... 9 Clock Outputs .......................................................................................................................... 12 Crystal Oscillator Input ............................................................................................................. 12 Termination of unused inputs and outputs .............................................................................. 14 Power Consumption ................................................................................................................ 15 Power Supply Filtering ............................................................................................................. 17 Device Control ......................................................................................................................... 17 Register Map ........................................................................................................................... 21 AC and DC Electrical Characteristics ...................................................................................... 26 Absolute Maximum Ratings ..................................................................................................... 26 Recommended Operating Conditions ..................................................................................... 26 Package Outline ...................................................................................................................... 33 February 2017 2 ZL40240 2017 Microsemi Corporation