1Gb: x16, x32 Automotive LPDDR2 SDRAM
Features
Automotive LPDDR2 SDRAM
EDB1332BD, EDB1316BD, EDB2432B4
Options Marking
Features
Density/Page Size
Ultra low-voltage core and I/O power supplies
1Gb/2KB - single die 13
V = 1.141.30V
DD2
2Gb/2KB - dual die 24
V /V = 1.141.30V
DDCA DDQ
Organization
V = 1.701.95V
DD1
x16 16
Clock frequency range
x32 32
53310 MHz (data rate range: 106620 Mb/s/pin)
V : 1.2V B
DD2
Four-bit prefetch DDR architecture
Revision
Eight internal banks for concurrent operation
Single die D
Multiplexed, double data rate, command/address
Multi-die 4
inputs; commands entered on every CK edge
FBGA green package
Bidirectional/differential data strobe per byte of
134-ball FBGA BH
data (DQS/DQS#)
134-ball multi-die FBGA MA
Programmable READ and WRITE latencies (RL/WL)
Timing cycle time
Programmable burst lengths: 4, 8, or 16
1.875ns @ RL = 8 -1D
Per-bank refresh for concurrent operation
Special options
On-chip temperature sensor to control self refresh
Automotive grade (Package-level A
rate (SR not supported >105C)
burn-in)
Partial-array self refresh (PASR)
1
Operating temperature range
Deep power-down mode (DPD)
From 40C to +85C IT
Selectable output drive strength (DS)
From 40C to +105C AT
Clock stop capability
2
From 40C to +125C UT
RoHS-compliant, green packaging
1. When T >105C, self-refresh mode is not
Notes:
C
available.
Table 1: Key Timing Parameters
2. UT option use based on automotive usage
model. Please contact Micron sales repre-
Speed Clock Rate Data Rate
sentative with questions.
t t
Grade (MHz) (Mb/s/pin) RL WL RCD/ RP
-1D 533 1066 8 4 Typical
Table 2: S4 Configuration Addressing
Architecture 64 Meg x 16 32 Meg x 32 64 Meg x 32
Die configuration 8 Meg x 16 x 8 banks 4 Meg x 32 x 8 banks 2 x 8 Meg x 16 x 8 banks
Row addressing 8K (A[12:0]) 8K (A[12:0]) 8K (A[12:0])
Column addressing 1K (A[9:0]) 512 (A[8:0]) 1K (A[9:0])
Number of die 1 1 2
Die per rank 1 1 2
1
Ranks per channel 111
1. A channel is a complete LPDRAM interface, including command/address and data pins.
Note:
09005aef86530ccb Micron Technology, Inc. reserves the right to change products or specifications without notice.
1
u98m_lpddr2_auto_at_ut.pdf - Rev. I 05/18 EN 2015 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.1Gb: x16, x32 Automotive LPDDR2 SDRAM
Features
Figure 1: LPDDR2 Part Numbering
E D B 13 32 B 4 BH -1D A AT -F
Embedded Memory Environment Code
-F = Lead free (RoHS compliant)
and halogen free
Type
D = Packaged device
Operating Temperature
IT = 40C to +85C
Product Family
AT = 40C to +105C
B = DDR2 Mobile RAM
UT = 40C to +125C
Density
Special Options
13 = 1Gb/2KB
A = Automotive grade
24 = 2Gb/2KB
Speed (package only)
Organization
-1D = 1066 Mbps
16 = x16
32 = x32
64 = x64 Package
BH = 134-ball VFBGA (10mm x 11.5mm)
MA = 134-ball VFBGA (10mm x 11.5mm)
Power Supply and Interface
B = V = 1.8V; V = V = 1.2V;
DD1 DD2 DDQ
Revision
S4B device; HSUL
D (for single-die)
4 (for multi-die)
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. Microns FBGA part marking decoder is available at www.micron.com/decoder.
Table 3: Package Codes and Descriptions
Package Die per Solder Ball
Code Ball Count # Ranks # Channels Size (mm) Package Composition
BH 134 1 1 10 x 11.5 x 1.0, 0.65 pitch SDP SAC302
MA 134 1 1 10 x 11.5 x 1.0, 0.65 pitch DDP SAC302
1. SDP = single-die package; DDP = Dual-die package
Notes:
2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).
09005aef86530ccb Micron Technology, Inc. reserves the right to change products or specifications without notice.
2
u98m_lpddr2_auto_at_ut.pdf - Rev. I 05/18 EN 2015 Micron Technology, Inc. All rights reserved.