Embedded LPDDR2 SDRAM Features Embedded LPDDR2 SDRAM EDB1316BD, EDB1332BD, EDB2432B4, EDB4064B4 Options Marking Features Density/Page Size Ultra low-voltage core and I/O power supplies 1Gb/2KB - single die 13 V = 1.141.30V DD2 2Gb/2KB - dual die 24 V /V = 1.141.30V DDCA DDQ 4Gb/2KB - quad die 40 V = 1.701.95V DD1 Organization Clock frequency range x16 16 53310 MHz (data rate range: 106620 Mb/s/pin) x32 32 Four-bit prefetch DDR architecture x64 64 Eight internal banks for concurrent operation V : 1.2V B DD2 Multiplexed, double data rate, command/address Revision inputs commands entered on every CK edge Single die D Bidirectional/differential data strobe per byte of Multi-die 4 data (DQS/DQS ) FBGA green package Programmable READ and WRITE latencies (RL/WL) 134-ball FBGA BH Programmable burst lengths: 4, 8, or 16 134-ball multi-die FBGA MA Per-bank refresh for concurrent operation 168-ball FBGA PC Partial-array self refresh (PASR) for PoP Deep power-down mode (DPD) 216-ball multi-die FBGA PB Selectable output drive strength (DS) for PoP Clock stop capability Timing cycle time RoHS-compliant, green packaging 1.875ns RL = 8 -1D Operating temperature range Table 1: Key Timing Parameters From 30C to +85C (Blank) From 40C to +85C IT Speed Clock Rate Data Rate Grade (MHz) (Mb/s/pin) RL WL 1D 533 1066 8 4 Table 2: S4 Configuration Addressing Architecture 64 Meg x 16 32 Meg x 32 64 Meg x 32 64 Meg x 64 Die configura- 8 Meg x 16 x 8 banks 4 Meg x 32 x 8 banks 2 x 8 Meg x 16 x 8 banks 4 x 8 Meg x 16 x 8 banks tion Row addressing 8K (A 12:0 ) 8K (A 12:0 ) 8K (A 12:0 ) 8K (A 12:0 ) Column ad- 1K (A 9:0 ) 512 (A 8:0 ) 1K (A 9:0 ) 1K (A 9:0 ) dressing Number of die 1 1 2 4 Die per rank 1 1 2 2 Ranks per chan- 1112 1 nel 1. A channel is a complete LPDRAM interface, including command/address and data pins. Note: X26P4QTWDSPK-13-10152 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1 u98m lpddr2 embedded.pdf - Rev. E 11/16 EN 2015 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.Embedded LPDDR2 SDRAM Features Figure 1: LPDDR2 Part Numbering E D B 13 32 B D BH -1D IT -F Embedded Memory Environment Code F = Lead-free (RoHS-compliant) and halogen-free Type D = Packaged device Operating Temperature Product Family IT = 40C to +85C Blank = 30C to +85C B = DDR2 Mobile RAM Density Speed (package only) 13 = 1Gb/2KB 1D = 1066 Mbps 24 = 2Gb/2KB 40 = 4Gb/2KB Package BH = 134-ball VFBGA (10mm x 11.5mm) MA = 134-ball VFBGA (10mm x 11.5mm) Organization PC = 168-ball WFBGA (12mm x 12mm) 16 = x16 32 = x32 PB = 216-ball WFBGA (12mm x 12mm) 64 = x64 Revision Power Supply and Interface D (for single-die) B = V = 1.8V V = V = 1.2V DD1 DD2 DDQ 4 (for multi-die) S4B device HSUL FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. Microns FBGA part marking decoder is available at www.micron.com/decoder. Table 3: Package Codes and Descriptions Package Die per Solder Ball Code Ball Count Ranks Channels Size (mm) Package Composition BH 134 1 1 10 x 11.5 x 1.0, 0.65 pitch SDP SAC302 MA 134 1 1 10 x 11.5 x 1.0, 0.65 pitch DDP SAC302 PC 168 1 1 12 x 12 x 0.8, 0.5 pitch SDP SAC302 PB 216 2 2 12 x 12 x 0.8, 0.4 pitch QDP SAC302 Notes: 1. SDP = single-die package DDP = Dual-die package QDP = Quad-die package . 2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu). X26P4QTWDSPK-13-10152 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2 u98m lpddr2 embedded.pdf - Rev. E 11/16 EN 2015 Micron Technology, Inc. All rights reserved.