Embedded LPDDR2 SDRAM
Features
Embedded LPDDR2 SDRAM
EDB4416BBBH, EDB4432BBBJ
Options Marking
Features
Density/Page Size
Ultra-low-voltage core and I/O power supplies
4Gb / 1-CS - single die 44
Frequency range
Organization
53310 MHz (data rate range: 106620 Mb/s/pin)
x16 16
4n prefetch DDR architecture
x32 32
8 internal banks for concurrent operation
V /V /V : 1.8V/1.2V/1.2V B
DD1 DD2 DDQ
Multiplexed, double data rate, command/address
Revision B
inputs; commands entered on each CK_t/CK_c
FBGA green package
edge
10mm x 11.5mm x 0.75mm, 134- BH
Bidirectional/differential data strobe per byte of
ball x16
data (DQS_t/DQS_c)
10mm x 11.5mm x 0.75mm, 134- BJ
Programmable READ and WRITE latencies (RL/WL)
ball x32
Burst length: 4, 8, and 16
Timing cycle time
Per-bank refresh for concurrent operation
1.875ns @ RL = 8 -1D
Auto temperature-compensated self refresh
Operating temperature range
(ATCSR) by built-in temperature sensor
From 30C to +85C Blank
Partial-array self refresh (PASR)
From 40C to +85C IT
Selectable output drive strength (DS)
Clock-stop capability
Lead-free (RoHS-compliant) and halogen-free
packaging
Table 1: Key Timing Parameters
Speed Clock Rate Data Rate
Grade (MHz) (Mb/s/pin) RL WL
1D 533 1066 8 4
Table 2: S4 Configuration Addressing
Architecture 256 Meg x 16 128 Meg x 32
Die configuration 32 Meg x 16 x 8 banks 16 Meg x 32 x 8 banks
Row addressing 16K A[13:0] 16K A[13:0]
Column addressing 2K A[10:0] 1K A[9:0]
X26P4QTWDSPK-13-10166 Micron Technology, Inc. reserves the right to change products or specifications without notice.
1
134b_2e0e_embedded_lpddr2 Rev. B 09/16 EN 2016 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.Embedded LPDDR2 SDRAM
Features
Figure 1: LPDDR2 Part Numbering
E D B 44 32 B B BH -1D IT -F
Embedded Memory Environment Code
F = Lead-free (RoHS-compliant)
and halogen-free
Type
D = Packaged device
Operating Temperature
IT = 40C to +85C
Product Family
Blank = 30C to +85C
B = DDR2 Mobile RAM
Density Speed (package only)
1D = 1066 Mbps
44 = 4Gb/1-CS
Organization Package
BH = 134-ball WFBGA (10mm x 11.5mm)
16 = x16
32 = x32 BJ = 134-ball WFBGA (10mm x 11.5mm)
Power Supply and Interface Revision
= V = 1.2V;
B = V = 1.8V; V
DDQ
DD1 DD2
S4B device; HSUL
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. Microns FBGA part marking decoder is available at www.micron.com/decoder.
Table 3: Package Codes and Descriptions
Package Die per Solder Ball
Code Ball Count # Ranks # Channels Size (mm) Package Composition
BH 134 1 1 (x16) 10 x 11.5 x 0.75, 0.65 pitch SDP SAC302
BJ 134 1 1 (x32) 10 x 11.5 x 0.75, 0.65 pitch SDP SAC302
Notes: 1. SDP = single-die package
2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).
X26P4QTWDSPK-13-10166 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2
134b_2e0e_embedded_lpddr2 Rev. B 09/16 EN 2016 Micron Technology, Inc. All rights reserved.