1GB, 2GB, 4GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
Features
DDR2 SDRAM RDIMM
MT18HTF12872PZ 1GB
MT18HTF25672PZ 2GB
MT18HTF51272PZ 4GB
Figure 1: 240-Pin RDIMM (MO-237 R/C H)
Features
240-pin, registered dual in-line memory module
Module height: 30mm (1.181in)
Fast data transfer rates: PC2-3200, PC2-4200,
PC2-5300, or PC2-6400
1GB (128 Meg x 72), 2GB (256 Meg x 72), 4GB (512
Meg x72)
Supports ECC error detection and correction
V = V = +1.8V
DD DDQ
Options Marking
V = 1.73.6V
DDSPD
Parity P
JEDEC-standard 1.8V I/O (SSTL_18-compatible)
Operating temperature
Differential data strobe (DQS, DQS#) option
None
Commercial (0C T +85C)
C
4n-bit prefetch architecture
1
I
Industrial (40C T +85C)
A
Single rank
Package
Multiple internal device banks for concurrent
240-pin DIMM (halogen-free) Z
2
operation
Frequency/CL
2.5ns @ CL = 5 (DDR2-800) -80E
Programmable CAS# latency (CL)
2.5ns @ CL = 6 (DDR2-800) -800
Posted CAS# additive latency (AL)
3.0ns @ CL = 5 (DDR2-667) -667
t
WRITE latency = READ latency - 1 CK
1. Contact Micron for industrial temperature
Notes:
Programmable burst lengths (BL): 4 or 8
module offerings.
Adjustable data-output drive strength
2. CL = CAS (READ) latency; registered mode
64ms, 8192-cycle refresh
will add one clock cycle to CL.
On-die termination (ODT)
Serial presence-detect (SPD) with EEPROM
Gold edge contacts
Halogen-free
Table 1: Key Timing Parameters
Data Rate (MT/s) t t t
Speed Industry RCD RP RC
Grade Nomenclature CL = 6 CL = 5 CL = 4 CL = 3 (ns) (ns) (ns)
-80E PC2-6400 800 800 533 400 12.5 12.5 55
-800 PC2-6400 800 667 533 400 15 15 55
-667 PC2-5300 667 553 400 15 15 55
-53E PC2-4200 553 400 15 15 55
-40E PC2-3200 400 400 15 15 55
PDF: 09005aef83dadad1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
1
htf18c128_256_512x72pz - Rev. C 1/11 EN 2010 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.1GB, 2GB, 4GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
Features
Table 2: Addressing
Parameter 1GB 2GB 4GB
Refresh count 8K 8K 8K
Row address 16K A[13:0] 16K A[13:0] 32K A[14:0]
Device bank address 4 BA[1:0] 8 BA[2:0] 8 BA[2:0]
Device configuration 512Mb (128 Meg x 4) 1Gb (256 Meg x 4) 2Gb (512 Meg x 4)
Column address 2K A[11, 9:0] 2K A[11, 9:0] 2K A[11, 9:0]
Module rank address 1 S0# 1 S0# 1 S0#
Table 3: Part Numbers and Timing Parameters 1GB
1
Base device: MT47H128M4, 512Mb DDR2 SDRAM
Module Module Memory Clock/ Clock Cycles
2 t t
Part Number Density Configuration Bandwidth Data Rate (CL- RCD- RP)
MT18HTF12872P(I)Z-80E__ 1GB 128 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 5-5-5
MT18HTF12872P(I)Z-800__ 1GB 128 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 6-6-6
MT18HTF12872P(I)Z-667__ 1GB 128 Meg x 72 5.3 GB/s 3.0ns/800 MT/s 5-5-5
Table 4: Part Numbers and Timing Parameters 2GB
1
Base device: MT47H256M4, 1Gb DDR2 SDRAM
Module Module Memory Clock/ Clock Cycles
2 t t
Part Number Density Configuration Bandwidth Data Rate (CL- RCD- RP)
MT18HTF25672P(I)Z-80E__ 2GB 256 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 5-5-5
MT18HTF25672P(I)Z-800__ 2GB 256 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 6-6-6
MT18HTF25672P(I)Z-667__ 2GB 256 Meg x 72 5.3 GB/s 3.0ns/800 MT/s 5-5-5
Table 5: Part Numbers and Timing Parameters 4GB
1
Base device: MT47H512M4, 2Gb DDR2 SDRAM
Module Module Memory Clock/ Clock Cycles
2 t t
Part Number Density Configuration Bandwidth Data Rate (CL- RCD- RP)
MT18HTF51272P(I)Z-80E__ 4GB 512 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 5-5-5
MT18HTF51272P(I)Z-800__ 4GB 512 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 6-6-6
MT18HTF51272P(I)Z-667__ 4GB 512 Meg x 72 5.3 GB/s 3.0ns/800 MT/s 5-5-5
1. Data sheets for the base device can be found on Microns Web site.
Notes:
2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Con-
sult factory for current revision codes. Example: MT18HTF25672PZ-667H1.
PDF: 09005aef83dadad1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2
htf18c128_256_512x72pz - Rev. C 1/11 EN 2010 Micron Technology, Inc. All rights reserved.