MT47H128M16RT-25E XIT:C TR Micron

2Gb: x4, x8, x16 DDR2 SDRAM Features DDR2 SDRAM MT47H512M4 64 Meg x 4 x 8 banks MT47H256M8 32 Meg x 8 x 8 banks MT47H128M16 16 Meg x 16 x 8 banks 1 Options Marking Features Configuration V = 1.8V 0.1V, V = 1.8V 0.1V DD DDQ 512 Meg x 4 (64 Meg x 4 x 8 banks) 512M4 JEDEC-standard 1.8V I/O (SSTL 18-compatible) 256 Meg x 8 (32 Meg x 8 x 8 banks) 256M8 Differential data strobe (DQS, DQS ) option 128 Meg x 16 (16 Meg x 16 x 8 banks) 128M16 FBGA package (Pb-free) x16 4n-bit prefetch architecture 84-ball FBGA (11.5mm x 14mm) Rev. A HG Duplicate output strobe (RDQS) option for x8 FBGA package (Pb-free) x4, x8 DLL to align DQ and DQS transitions with CK 60-ball FBGA (11.5mm x 14mm) Rev. A HG 8 internal banks for concurrent operation FBGA package (Pb-free) x16 Programmable CAS latency (CL) 84-ball FBGA (9mm x 12.5mm) Rev. C RT Posted CAS additive latency (AL) FBGA package (Pb-free) x4, x8 t 60-ball FBGA (9mm x 11.5mm) Rev. C EB WRITE latency = READ latency - 1 CK FBGA package (Lead solder) x16 Programmable burst lengths: 4 or 8 84-ball FBGA (9mm x 12.5mm) Rev. C PK Adjustable data-output drive strength Timing cycle time 64ms, 8192-cycle refresh 1.875ns CL = 7 (DDR2-1066) -187E On-die termination (ODT) 2.5ns CL = 5 (DDR2-800) -25E Industrial temperature (IT) option 2.5ns CL = 6 (DDR2-800) -25 3.0ns CL = 5 (DDR2-667) -3 RoHS-compliant Self refresh Supports JEDEC clock jitter specification Standard None Operating temperature Commercial (0C T +85C) None C Industrial (40C T +95C IT C 40C T +85C) A Revision :A/:C 1. Not all options listed can be combined to Note: define an offered product. Use the Part Catalog Search on www.micron.com for product offerings and availability. CCMTD-1725822587-6523 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1 2Gb DDR2.pdf Rev. J 09/18 EN 2006 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.2Gb: x4, x8, x16 DDR2 SDRAM Features Table 1: Key Timing Parameters Data Rate (MHz) t Speed Grade CL = 3 CL = 4 CL = 5 CL = 6 CL = 7 RC (ns) -187E 400 533 800 800 1066 54 -25E 400 533 800 800 n/a 55 -25 400 533 667 800 n/a 55 -3 400 533 667 n/a n/a 55 Table 2: Addressing Parameter 512 Meg x 4 256 Meg x 8 128 Meg x 16 Configuration 64 Meg x 4 x 8 banks 32 Meg x 8 x 8 banks 16 Meg x 16 x 8 banks Refresh count 8K 8K 8K Row address A 14:0 (32K) A 14:0 (32K) A 13:0 (16K) Bank address BA 2:0 (8) BA 2:0 (8) BA 2:0 (8) Column address A 11, 9:0 (2K) A 9:0 (1K) A 9:0 (1K) Part Numbers Figure 1: 2Gb DDR2 Part Numbers Example Part Number: MT47H256M8EB-25 :C - : MT47H Configuration Package Speed Revision :A/:C Configuration Revision 512 Meg x 4 512M4 256 Meg x 8 256M8 IT Industrial Temperature 128 Meg x 16 128M16 Power Package Standard Blank HG 84-Ball 11.5mm x 14mm FBGA Speed Grade 60-Ball 11.5mm x 14mm FBGA HG t -187E CK = 1.875ns, CL = 7 RT 84-Ball 9.0mm x 12.5mm FBGA t -25E CK = 2.5ns, CL = 5 EB 60-Ball 9.0mm x 11.5mm FBGA t -25 CK = 2.5ns, CL = 6 PK 84-Ball 9.0mm x 12.5mm FBGA (lead solder) t -3 CK = 3ns, CL = 5 1. Not all speeds and configurations are available. Note: FBGA Part Number System Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Microns Web site: