512Mb: x8, x16 Automotive DDR2 SDRAM Features Automotive DDR2 SDRAM MT47H64M8 16 Meg x 8 x 4 banks MT47H32M16 8 Meg x 16 x 4 banks 1 Options Marking Features Configuration V = 1.8V 0.1V, V = 1.8V 0.1V DD DDQ 64 Meg x 8 (16 Meg x 8 x 4 banks) 64M8 JEDEC-standard 1.8V I/O (SSTL 18-compatible) 32 Meg x 16 (8 Meg x 16 x 4 banks) 32M16 Differential data strobe (DQS, DQS ) option FBGA package (Pb-free) x16 84-ball FBGA (8mm x 12.5mm) Rev. H NF 4n-bit prefetch architecture FBGA package (Pb-free) x8 Duplicate output strobe (RDQS) option for x8 60-ball FBGA (8mm x 10mm) Rev. H SH DLL to align DQ and DQS transitions with CK Timing cycle time 4 internal banks for concurrent operation 2.5ns CL = 5 (DDR2-800) -25E Programmable CAS latency (CL) 2.5ns CL = 6 (DDR2-800) -25 Posted CAS additive latency (AL) 3.0ns CL = 4 (DDR2-667) -3E t 3.0ns CL = 5 (DDR2-667) -3 WRITE latency = READ latency - 1 CK Special options Selectable burst lengths: 4 or 8 Standard None Adjustable data-output drive strength Automotive grade A 64ms, 8192-cycle refresh Operating temperature On-die termination (ODT) Industrial (40C T +95C IT C RoHS-compliant 40C T +85C) A Automotive (40C T +105C) AT Supports JEDEC clock jitter specification C Revision :H AEC-Q100 1. Not all options listed can be combined to PPAP submission Note: define an offered product. Use the Part 8D response time Catalog Search on www.micron.com for product offerings and availability. PDF: 09005aef859d78b5 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1 512MbDDR2 automotive.pdf - Rev. C 06/18 EN 2014 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.512Mb: x8, x16 Automotive DDR2 SDRAM Features Table 1: Key Timing Parameters Data Rate (MT/s) t Speed Grade CL = 3 CL = 4 CL = 5 CL = 6 CL = 7 RC (ns) -25E 400 533 800 800 n/a 55 -25 400 533 667 800 n/a 55 -3E 400 667 667 n/a n/a 54 -3 400 533 667 n/a n/a 55 Table 2: Addressing Parameter 64 Meg x 8 32 Meg x 16 Configuration 16 Meg x 8 x 4 banks 8 Meg x 16 x 4 banks Refresh count 8K 8K Row address A 13:0 (16K) A 12:0 (8K) Bank address BA 1:0 (4) BA 1:0 (4) Column address A 9:0 (1K) A 9:0 (1K) Figure 1: 512Mb DDR2 Part Numbers MT 47 H 32M16 NF -25E A IT :H Micron Technology Design Revision :H = Design generation Product Family 47 = DDR SDRAM Operating Temperature IT = Industrial (40C to +85C) Operating Voltage AT = Automotive (40C to +105C) H = 1.8V V CMOS DD Special Options Configuration (depth, width) (Multiple processing codes are separated 64 Meg x 8 = 64M8 by a space and are listed in hierarchical order.) 32 Meg x 16 = 32M16 Blank = None A = Automotive 1 Package Codes Pb-free Speed Grade t NF = 84-ball 8mm x 12.5mm FBGA -3 = 3ns CK, CL = 5 t SH = 60-ball 8mm x 10.00mm FBGA -3E = 3ns CK, CL = 4 t -25 = 2.5ns CK, CL = 6 t -25E = 2.5ns CK, CL = 5 1. Not all speeds and configurations are available in all packages. Note: PDF: 09005aef859d78b5 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2 512MbDDR2 automotive.pdf - Rev. C 06/18 EN 2014 Micron Technology, Inc. All rights reserved.