MT48H32M16LFB4-6 AT:C TR Micron

512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Features Mobile LPSDR SDRAM MT48H32M16LF 8 Meg x 16 x 4 Banks MT48H16M32LF/LG 4 Meg x 32 x 4 Banks Options Marking Features V /V : 1.8V/1.8V H DD DDQ V /V = 1.71.95V DD DDQ Addressing Fully synchronous all signals registered on positive Standard addressing option LF 1 edge of system clock Reduced page size option LG Internal, pipelined operation column address can Configuration be changed every clock cycle 32 Meg x 16 (8 Meg x 16 x 4 32M16 banks) Four internal banks for concurrent operation 16 Meg x 32 (4 Meg x 32 x 4 16M32 Programmable burst lengths: 1, 2, 4, 8, and continu- banks) ous Plastic green packages Auto precharge, includes concurrent auto precharge 2 54-ball VFBGA (8mm x 8mm) B4 Auto refresh and self refresh modes 3 90-ball VFBGA (8mm x 13mm) B5 LVTTL-compatible inputs and outputs Timing cycle time On-chip temperature sensor to control self refresh 6ns at CL = 3 -6 rate 7.5ns at CL = 3 -75 Power Partial-array self refresh (PASR) Standard I /I None DD2 DD7 Deep power-down (DPD) 1 Low-power I /I L DD2 DD7 Selectable output drive strength (DS) Operating temperature range 64ms refresh period 32ms for automotive tempera- Commercial (0C to +70C) None ture Industrial (40C to +85C) IT Automotive (40C to +105C) AT Revision :C 1. Contact factory for availability. Notes: 2. Available only for x16 configuration. 3. Available only for x32 configuration. Table 1: Configuration Addressing 16 Meg x 32 Reduced 1 Architecture 32 Meg x 16 16 Meg x 32 Page Size Option Number of banks 4 4 4 Bank address balls BA0, BA1 BA0, BA1 BA0, BA1 Row address balls A 12:0 A 12:0 A 13:0 Column address balls A 9:0 A 8:0 A 7:0 1. Contact factory for availability. Note: PDF: 09005aef8459c827 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1 512mb mobile sdram y67m at.pdf Rev. C 10/2018 EN 2011 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Features Table 2: Key Timing Parameters Clock Rate (MHz) Access Time Speed Grade CL = 2 CL = 3 CL = 2 CL = 3 -6 104 166 8ns 5ns -75 104 133 8ns 5.4ns Note: 1. CL = CAS (READ) latency. Figure 1: 512Mb Mobile LPSDR Part Numbering MT 48 H 32M16 LF B4 -75 IT :C Design Revision Micron Technology :C = Device generation Product Family Operating Temperature 48 = Mobile LPSDR SDRAM Blank = Commercial (0C to +70C) IT = Industrial (40C to +85C) Operating Voltage AT = Automotive (40C to +105C) H = 1.8V/1.8V Low Power Configuration Blank = Standard I /I 32M16 = 32 Meg x 16 DD2 DD7 L = Low-power I /I 16M32 = 16 Meg x 32 DD2 DD7 Cycle Time Addressing t -6 = 6ns, CK CL = 3 LF = Standard addressing t -75 = 7.5ns, CK CL = 3 LG = Reduced page size Package Codes B4 = 8mm x 8mm, VFBGA, green B5 = 8mm x 13mm, VFBGA, green FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. Microns FBGA part marking decoder is available at www.micron.com/decoder. PDF: 09005aef8459c827 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2 512mb mobile sdram y67m at.pdf Rev. C 10/2018 EN 2011 Micron Technology, Inc. All rights reserved.