MT40A256M16GE-083E AUT:B TR Micron

4Gb: x8, x16 Automotive DDR4 SDRAM Features Automotive DDR4 SDRAM MT40A512M8 MT40A256M16 JEDEC JESD-79-4 compliant Features AEC-Q100 V = V = 1.2V 60mV DD DDQ PPAP submission V = 2.5V 125mV/+250mV PP 8D response time On-die, internal, adjustable V generation REFDQ 1 Options Marking 1.2V pseudo open-drain I/O Configuration Refresh maximum interval time at T temperature C 512 Meg x 8 512M8 range: 256 Meg x 16 256M16 64ms at 40C to 85C BGA package (Pb-free) x8 32ms at 85C to 95C 78-ball (9mm x 10.5mm) Rev. B RH 16ms at 96C to 105C FBGA package (Pb-free) x16 8ms at 106C to 125C 96-ball (9mm x 14mm) Rev. B GE 16 internal banks ( x8): 4 groups of 4 banks each Timing cycle time 8 internal banks (x16): 2 groups of 4 banks each 0.750ns CL = 18 (DDR4-2666) -075E 8n-bit prefetch architecture 0.833ns CL = 16 (DDR4-2400) -083E Programmable data strobe preambles Product certification Data strobe preamble training Automotive A Command/Address latency (CAL) Operating temperature Multipurpose register read and write capability Industrial (40C T +95C) IT Write leveling C Automotive (40C T +105C) AT Self refresh mode C 3 Ultra-high (40C T +125C) UT Low-power auto self refresh (LPASR) C Revision :B Temperature controlled refresh (TCR) Fine granularity refresh 1. Not all options listed can be combined to Notes: Self refresh abort define an offered product. Use the part Maximum power saving catalog search on 4Gb: x8, x16 Automotive DDR4 SDRAM Features Table 1: Key Timing Parameters t t t t Speed Grade Data Rate (MT/s) Target RCD- RP-CL RCD (ns) RP (ns) CL (ns) 1 -075E 2666 18-18-18 13.5 13.5 13.5 -083E 2400 16-16-16 13.32 13.32 13.32 Note: 1. Backward compatible to 2400, CL = 16 Table 2: Addressing Parameter 512 Meg x 8 256 Meg x 16 Number of bank groups 4 2 Bank group address BG 1:0 BG0 Bank count per group 4 4 Bank address in bank group BA 1:0 BA 1:0 Row addressing 32K (A 14:0 ) 32K (A 14:0 ) Column addressing 1K (A 9:0 ) 1K (A 9:0 ) 1 Page size 1KB 2KB Note: 1. Page size is per bank, calculated as follows: COLBITS Page size = 2 ORG/8, where COLBIT = the number of column address bits and ORG = the number of DQ bits. Figure 1: Order Part Number Example Example Part Number: MT40A512M8RH-075EAAT:B - : Configuration Package Speed Revision MT40A Revision Configuration Mark :B 512 Meg x 8 512M8 256 Meg x 16 256M16 Case Temperature Mark Commercial Package Mark None 78-ball 8.0mm x 10.5mm FBGA RH Industrial temperature IT Automotive AT 96-ball 9.0mm x 14.0mm FBGA GE Ultra-high UT Mark Speed Grade t -075E CK = 0.750ns, CL = 18 Product certification Mark t -083E CK = 0.833ns, CL = 16 Automotive A CCMTD-1725822587-10418 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2 4gb auto ddr4 sdram z90b.pdf - Rev. G 08/18 EN 2016 Micron Technology, Inc. All rights reserved.