8Gb: x4, x8, x16 DDR4 SDRAM
Features
DDR4 SDRAM
MT40A2G4
MT40A1G8
MT40A512M16
1
Options Marking
Features
Configuration
V = V = 1.2V 60mV
DD DDQ
2 Gig x 4 2G4
V = 2.5V, 125mV, +250mV
PP
1 Gig x 8 1G8
On-die, internal, adjustable V generation
REFDQ
512 Meg x 16 512M16
1.2V pseudo open-drain I/O
78-ball FBGA package (Pb-free) x4,
T maximum up to 95C
C
x8
64ms, 8192-cycle refresh up to 85C
9mm x 13.2mm Rev. A PM
32ms, 8192-cycle refresh at >85C to 95C
8mm x 12mm Rev. B, D, G WE
16 internal banks (x4, x8): 4 groups of 4 banks each
7.5mm x 11mm Rev. E, H, J SA
8 internal banks (x16): 2 groups of 4 banks each
96-ball FBGA package (Pb-free) x16
8n-bit prefetch architecture
9mm x 14mm Rev. A HA
Programmable data strobe preambles
8mm x 14mm Rev. B JY
Data strobe preamble training
7.5mm x 13.5mm Rev. D, E, H LY
Command/Address latency (CAL)
7.5mm x 13mm Rev. J TB
Multipurpose register READ and WRITE capability
Timing cycle time
Write leveling
0.625ns @ CL = 22 (DDR4-3200) -062E
Self refresh mode
0.682ns @ CL = 21 (DDR4-2933) -068
Low-power auto self refresh (LPASR)
0.750ns @ CL = 19 (DDR4-2666) -075
Temperature controlled refresh (TCR)
0.750ns @ CL = 18 (DDR4-2666) -075E
Fine granularity refresh
0.833ns @ CL = 17 (DDR4-2400) -083
Self refresh abort
0.833ns @ CL = 16 (DDR4-2400) -083E
Maximum power saving
0.937ns @ CL = 15 (DDR4-2133) -093E
Output driver calibration
1.071ns @ CL = 13 (DDR4-1866) -107E
Nominal, park, and dynamic on-die termination
Operating temperature
(ODT)
Commercial (0 T 95C) None
C
Data bus inversion (DBI) for data bus
Industrial (40 T 95C) IT
C
Command/Address (CA) parity
Revision :A, :B, :D, :E,
Databus write cyclic redundancy check (CRC)
:G, :H, :J
Per-DRAM addressability
1. Not all options listed can be combined to
Note:
Connectivity test
define an offered product. Use the part
JEDEC JESD-79-4 compliant
catalog search on 8Gb: x4, x8, x16 DDR4 SDRAM
Features
Table 1: Key Timing Parameters (Continued)
1 t t t t
Speed Grade Data Rate (MT/s) Target CL- RCD- RP CL (ns) RCD (ns) RP (ns)
-075 2666 19-19-19 14.25 14.25 14.25
-083E 2400 16-16-16 13.32 13.32 13.32
-083 2400 17-17-17 14.16 (13.75) 14.16 (13.75) 14.16 (13.75)
-093E 2133 15-15-15 14.06 (13.50) 14.06 (13.50) 14.06 (13.50)
-093 2133 16-16-16 15.00 15.00 15.00
-107E 1866 13-13-13 13.92 (13.50) 13.92 (13.50) 13.92 (13.50)
Note: 1. Refer to the Speed Bin Tables for additional details.
Table 2: Addressing
Parameter 2048 Meg x 4 1024 Meg x 8 512 Meg x 16
Number of bank groups 4 4 2
Bank group address BG[1:0] BG[1:0] BG0
Bank count per group 4 4 4
Bank address in bank group BA[1:0] BA[1:0] BA[1:0]
Row addressing 128K (A[16:0]) 64K (A[15:0]) 64K (A[15:0])
Column addressing 1K (A[9:0]) 1K (A[9:0]) 1K (A[9:0])
1 2
Page size 512B/1KB 1KB 2KB
Notes: 1. Page size is per bank, calculated as follows:
COLBITS
Page size = 2 ORG/8, where COLBIT = the number of column address bits and ORG = the number of
DQ bits.
2. Die rev-dependent.
CCMTD-1725822587-9875 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2
8gb_ddr4_dram.pdf - Rev. O 10/18 EN 2015 Micron Technology, Inc. All rights reserved.