1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Features
DDR2 SDRAM UDIMM
MT8HTF12864AZ 1GB
Figure 1: 240-Pin UDIMM (MO-237 R/C D)
Features
Module height: 30mm (1.181in)
240-pin, unbuffered dual in-line memory module
Fast data transfer rates: PC2-3200, PC2-4200,
PC2-5300, PC2-6400, or PC2-8500
1GB (128 Meg x 64)
V = V = 1.8V
DD DDQ
V = 1.73.6V
DDSPD
Options Marking
JEDEC-standard 1.8V I/O (SSTL_18-compatible)
1
Operating temperature
Differential data strobe (DQS, DQS#) option
Commercial (0C T +70C) None
A
4n-bit prefetch architecture
I
Industrial (40C T +85C)
A
Multiple internal device banks for concurrent
Package
operation
240-pin DIMM (halogen-free) Z
2
Programmable CAS latency (CL) Frequency/CL
3
1.875ns @ CL = 7 (DDR2-1066) -1GA
Posted CAS additive latency (AL)
2.5ns @ CL = 5 (DDR2-800) -80E
t
WRITE latency = READ latency - 1 CK
2.5ns @ CL = 6 (DDR2-800) -800
Programmable burst lengths (BL): 4 or 8
3.0ns @ CL = 5 (DDR2-667) -667
Adjustable data-output drive strength
Notes: 1. Contact Micron for industrial temperature
64ms, 8192-cycle refresh
module offerings.
On-die termination (ODT)
2. CL = CAS (READ) latency.
Serial presence detect (SPD) with EEPROM
3. Not recommended for new designs.
Gold edge contacts
Single rank
Table 1: Key Timing Parameters
Data Rate (MT/s) t t t
Speed Industry RCD RP RC
Grade Nomenclature CL = 7 CL = 6 CL = 5 CL = 4 CL = 3 (ns) (ns) (ns)
-1GA PC2-8500 1066 800 667 533 400 13.125 13.125 58.125
-80E PC2-6400 800 800 533 400 12.5 12.5 57.5
-800 PC2-6400 800 667 533 400 15 15 60
-667 PC2-5300 667 553 400 15 15 60
-53E PC2-4200 553 400 15 15 55
-40E PC2-3200 400 400 15 15 55
PDF: 09005aef83b94f21 Micron Technology, Inc. reserves the right to change products or specifications without notice.
1
htf8c128x64az Rev. B 3/10 EN 2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Features
Table 2: Addressing
Parameter 1GB
Refresh count 8K
Row address 16K A[13:0]
Device bank address 8 BA[2:0]
Device configuration 1Gb (128 Meg x 8)
Column address 1K A[9:0]
Module rank address 1 S0#
Table 3: Part Numbers and Timing Parameters 1GB Modules
1
Base device: MT47H128M8, 1Gb DDR2 SDRAM
Module Module Memory Clock/ Clock Cycles
2 t t
Part Number Density Configuration Bandwidth Data Rate (CL- RCD- RP)
MT8HTF12864A(I)Z-1GA__ 1GB 128 Meg x 64 8.5 GB/s 1.875ns/1066 MT/s 7-7-7
MT8HTF12864A(I)Z-80E__ 1GB 128 Meg x 64 6.2 GB/s 2.5ns/800 MT/s 5-5-5
MT8HTF12864A(I)Z-800__ 1GB 128 Meg x 64 6.2 GB/s 2.5ns/800 MT/s 6-6-6
MT8HTF12864A(I)Z-667__ 1GB 128 Meg x 64 5.3 GB/s 3.0ns/667 MT/s 5-5-5
1. The data sheet for the base device can be found on Microns Web site.
Notes:
2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions.
Consult factory for current revision codes. Example: MT8HTF12864AZ-800H1.
PDF: 09005aef83b94f21 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2
htf8c128x64az Rev. B 3/10 EN 2003 Micron Technology, Inc. All rights reserved.