74AHC139PW Nexperia

74AHC139 74AHCT139 Dual 2-to-4 line decoder/demultiplexer Rev. 02 9 May 2008 Product data sheet 1. General description The 74AHC139 74AHCT139 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specied in compliance with JEDEC standard No. 7-A. The 74AHC139 74AHCT139 is a high-speed, dual 2-to-4 line decoder/demultiplexer. This device has two independent decoders, each accepting two binary weighted inputs (nA0 and nA1) and providing four mutually exclusive active LOW outputs (nY0 to nY3). Each decoder has an active LOW enable input (nE). When nE is HIGH, every output is forced HIGH. The enable input can be used as the data input for a 1-to-4 demultiplexer application. The 74AHC139 74AHCT139 is identical to the HEF4556 of the HE4000B family. 2. Features n Balanced propagation delays n All inputs have Schmitt-trigger actions n Inputs accept voltages higher than V CC n Input levels: u For 74AHC139: CMOS level u For 74AHCT139: TTL level n ESD protection: u HBM EIA/JESD22-A114E exceeds 2000 V u MM EIA/JESD22-A115-A exceeds 200 V u CDM EIA/JESD22-C101C exceeds 1000 V n Multiple package options n Specied from - 40 C to +85 C and from - 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC139 74AHC139D - 40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74AHC139PW - 40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm74AHC139 74AHCT139 NXP Semiconductors Dual 2-to-4 line decoder/demultiplexer Table 1. Ordering information continued Type number Package Temperature range Name Description Version 74AHCT139 74AHCT139D - 40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74AHCT139PW - 40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 4. Functional diagram 1 1E 4 4 DX X/Y 4 0 0 2 2 1Y0 0 5 1 5 0 1 1 2 5 G 3 3 1A0 1Y1 3 1 6 2 6 3 6 2 2 1 1 1A1 1Y2 7 EN 7 7 3 3 1Y3 12 2Y0 12 12 DX X/Y 14 11 0 0 14 14 2A0 2Y1 0 11 1 11 0 13 10 1 1 G 13 13 2A1 2Y2 3 1 10 2 10 9 2 2 15 15 2Y3 9 EN 9 2E 3 3 15 (a) (b) mna779 mna781 a = demultiplexer and b = decoder Fig 1. Logic symbol Fig 2. IEC logic symbol 1Y0 4 2 1A0 1Y1 5 DECODER 3 1A1 1Y2 6 1Y3 7 1 1E 2Y0 12 2A0 14 2Y1 11 DECODER 13 2A1 2Y2 10 2Y3 9 2E 15 mna780 Fig 3. Functional diagram 74AHC AHCT139 2 NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 9 May 2008 2 of 14